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| Number | Title | Issue Date |
| 7734674 | Fast fourier transform (FFT) architecture in a multi-mode wireless processing system A system and method Fast Fourier Transform (FFT) method in a multi-mode wireless processing system. The method can include loading an input vector into an input buffer, initializing a second counter and a variable N, where N=log2 (input vector size), and ... | 06/08/2010 |
| 7325123 | Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements An integrated circuit having computational elements. As least one of the computational elements has a fixed architecture. An interconnection network is coupled to a first group of the computational elements to configure the first group for a first operation. An inte... | 01/29/2008 |
| 7242710 | Aliasing reduction using complex-exponential modulated filterbanks The present invention proposes a new method and apparatus for the improvement of digital filterbanks, by a complex extension of cosine modulated digital filterbanks. The invention employs complex-exponential modulation of a low-pass prototype filter and a new method... | 07/10/2007 |
| 7233968 | Fast fourier transform apparatus A data transform system performs FFT and IFFT computations with respect to N data points. The data transform system performs radix-R (R is an integer) butterfly computation in parallel by use of M arithmetic elements. Serial and parallel computation structures a rec... | 06/19/2007 |
| 7200194 | Receiver signal dynamic range compensation based on received signal strength indicator A method for processing a received signal at a mobile receiver of a wireless communications system is disclosed. The method comprises demodulating the received signal to obtain an analog base band signal and converting the analog base band signal into a digital base... | 04/03/2007 |
| 7197095 | Inverse fast fourier transform (IFFT) with overlap and add A system for efficiently filtering interfering signals in a front end of a GPS receiver is disclosed. Such interfering signals can emanate from friendly, as well as unfriendly, sources. One embodiment includes a GPS receiver with a space-time adaptive processing (ST... | 03/27/2007 |
| 7164723 | Modulation apparatus using mixed-radix fast fourier transform An FFT (Fast Fourier Transform) processor is disclosed which is a core block of an OFDM (Orthogonal Frequency Division Multiplexing) or DMT (Discrete Multi-tone) MODEM. The FFT processor simultaneously performs sequential input and output by applying an in-place alg... | 01/16/2007 |
| 6963891 | Fast fourier transform A fast Fourier transform with sequential memory accessing within each stage. ... | 11/08/2005 |
| 6631167 | Process and device for transforming real data into complex symbols, in particular for the reception of phase-modulated and amplitude-modulated carriers transmitted on a telephone line The post-processing of the transformation processing of an interleaved type is temporally nested with regards to two successive symbols, and includes storage in two separately addressable memories of identical size. The addressing of the two memories is p... | 10/07/2003 |
| 6408319 | Electronic device for computing a fourier transform and corresponding control process An electronic device for computing a Fourier transform having a pipeline architecture includes at least one processing stage with a radix equal to 4. Each processing stage includes elementary processing for performing process operations for Fourier transf... | 06/18/2002 |
| 6366936 | Pipelined fast fourier transform (FFT) processor having convergent block floating point (CBFP) algorithm A pipelined FFT (fast Fourier transform) processor including a CBFP (convergent block floating point) algorithm, includes an inverse multiplexer for inverse-multiplexing an 8K-/2K-point input data, a first to sixth radix-4 operation circuit for receiving ... | 04/02/2002 |
| 6330580 | Pipelined fast fourier transform processor A pipelined Fast Fourier Transform Processor includes, besides a memory arrangement, a cascade of a first arithmetic unit, a scratch memory and a second arithmetic unit. One of both arithmetic units can only perform at least one type of butterfly Fast Fou... | 12/11/2001 |
| 6324561 | Process and device for computing a fourier transform having a "pipelined" architecture For each input block of N data bits received as an input to a stage for computing a Fourier transform, only three quarters of the data bits of the input block are stored in a main storage. A Fourier transform computation is performed on the basis of the s... | 11/27/2001 |
| 6098088 | Real-time pipeline fast fourier transform processors A real-time pipeline processor, which is particularly suited for VLSI implementation, is based on a hardware oriented radix-22 algorithm derived by integrating a twiddle factor decomposition technique in a divide and conquer approach. The radix... | 08/01/2000 |
| 6061705 | Power and area efficient fast fourier transform processor A fast Fourier transform (FFT) processor is constructed using discrete Fourier transform (DFT) butterfly modules having, in preferred example embodiments, sizes greater than 4. In a first example embodiment, the FFT processor employs size-8 butterflies. I... | 05/09/2000 |
| 5845093 | Multi-port digital signal processor A digital signal processor on an integrated circuit uses a multi-port data flow structure characterized by four ports, referred to as an acquisition port, two data ports, and a coefficient port. All four ports may be bidirectional so that data may be read... | 12/01/1998 |
| 5473556 | Digit reverse for mixed radix FFT A digit reversing system is disclosed for handling mixed radix FFT operations with arbitrary arrangements of radices. In a first step, all bits in an integer field of size log2 N are position reversed. In a second step, subfields of the output ... | 12/05/1995 |
| 5313413 | Apparatus and method for preventing I/O bandwidth limitations in fast fourier transform processors A Quasi Radix-16 Butterfly comprises an radix-4 butterfly processor and on-board memory with external memory addressing changes from a conventional radix-4 butterfly processor. On-chip cache memory is included to store data outputs of the radix-4 butterfl... | 05/17/1994 |
| 5293330 | Pipeline processor for mixed-size FFTs A method is described for performing fast Fourier transforms (FFTs) of various sizes simultaneously in one pipeline processor. The processor consists of several stages of butterfly computational elements alternated with delay-switch-delay (DSD) modules th... | 03/08/1994 |
| 5233551 | Radix-12 DFT/FFT building block Using classic Fast Fourier Transform (FFT) rules, a radix-12 FFT is composed of a first tier of 2 multiplierless radix-6 transformers followed by multiplierless radix-2 transformers, or by its transpose configuration. Complex data are represented in a 1, ... | 08/03/1993 |
| 5091875 | Fast fourier transform (FFT) addressing apparatus and method Apparatus for generating memory addresses for accessing and storing data in an FFT (Fast Fourier Transform) computation is provided. The FFT computation is typically performed by computing a plurality of FFT butterflies belonging to a plurality of ranks. ... | 02/25/1992 |
| 5029079 | Apparatus and method for flexible control of digital signal processing devices A control apparatus for use with a digital signal processing device and associated memory units is described. The control apparatus determines, along with the electrical configuration of the digital signal processing device and associated memory units, th... | 07/02/1991 |
| 4868776 | Fast fourier transform architecture using hybrid n-bit-serial arithmetic A fast Fourier transform circuit, including an illustrative radix-eight discrete Fourier transform (DFT) kernel that operates on an n-bit-serial data format, for an efficient serial-like, pipelined operation within the DFT. The circuit performs a four-poi... | 09/19/1989 |
| 4791590 | High performance signal processor A monolithic high performance processor for computing digital signal processing algorithms based on the Fast Fourier Transform. The monolithic processor employs an array of bit-serial multipliers which cooperate with bit-serial adder/substractors to produ... | 12/13/1988 |
| 4768159 | Squared-radix discrete Fourier transform A radix-N2 or radix-N4 discrete Fourier transform (DFT) processor having cascaded stages alternately comprising N2 -sample memories and radix-N DFT's. Data is written into and read from the memories in a sequence permittin... | 08/30/1988 |
| 4694416 | VLSI programmable digital signal processor Method and apparatus are provided for performing a plurality of digital signal processing functions wherein each said function is a unique combination of identical subfunctions. A plurality of operating units are provided wherein each operating unit is ad... | 09/15/1987 |
| 4689762 | Dynamically configurable fast Fourier transform butterfly circuit A decimation-in-frequency fast-Fourier-transform butterfly circuit for performing a radix-four butterfly operation includes a first group of adders (86, 88, 90, and 92), a second group of adders (70, 72, 74, and 76), and a group of twiddle-factor multipli... | 08/25/1987 |
