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| Number | Title | Issue Date |
| 7984092 | FIR filter process and FIR filter arrangement The present invention relates to a FIR filter process (1′) and to a respective FIR filter arrangement (1) wherein at least one multiplex mode is given which is characterized in that in the respective summation stage (30′) or summation block ... | 07/19/2011 |
| 7636746 | Methods and systems for efficient filtering of digital signals A method in a signal processor for filtering samples in a digital signal is provided. An approximate filtered sample is generated as a function of eight samples of the digital signal. A correction is generated as a function of the eight samples, and a filtered sampl... | 12/22/2009 |
| 7412471 | Discrete filter having a tap selection circuit A digital signal processing circuit includes a chain of processing units having a selectable number of taps and a tap selection circuit. The tap selection circuit is coupled to the chain of processing units to establish the number of taps of the chains. ... | 08/12/2008 |
| 7409417 | Polyphase filter with optimized silicon area A polyphase filter including M taps, each of the M taps including a filter coefficient. The filter also includes a multiplier-accumulator (MAC) shared by the M taps, a plurality of multiplexors for sequentially selecting a subset of the plurality of taps, and a sche... | 08/05/2008 |
| 7366747 | Digital filter circuit and data processing method A digital filter circuit is capable of processing multi-channel data having different sampling frequencies. RAMs (random access memories) are provided which store data inputted thereto respectively, and the data outputted from the RAMs are alternately processed.... | 04/29/2008 |
| 7353243 | Reconfigurable filter node for an adaptive computing machine A reconfigurable filter node including an input data memory adapted to store a plurality of input data values, a filter coefficient memory adapted to store a plurality of filter coefficient values, and a plurality of computational units adapted to simultaneously com... | 04/01/2008 |
| 7334010 | Feedback digital filter A digital filter includes a data storage section, a filter coefficient storage section, a multiplier, an accumulative adder section, a data output section and a control section. The data storage section stores the latest multiple input data for every channel and out... | 02/19/2008 |
| 7330917 | Decimation of fixed length queues having a number of position for holding data wherein new data is favored over old data Decimation of data from a fixed length queue retaining a representative sample of the old data. Exponential decimation removes every nth sample. Dithered exponential decimation offsets the exponential decimation approach by a probabilistic amount. Recursive decimati... | 02/12/2008 |
| 7277479 | Reconfigurable fir filter A series of digit processing units (DPUs) are connected to form a finite impulse response (FIR) filter. Each DPU includes a register, a multiplexer, and a coefficient multiplier. The register stores and delays an input digital signal to be filtered. The multiplexer ... | 10/02/2007 |
| 7254598 | Finite impulse response filter and digital signal receiving apparatus An A/D conversion section performs oversampling on an analog signal at a rate M times a symbol rate to convert the analog signal into a digital signal. A FIR filtering section has two delay-element sequences, each with a plurality of delay elements. The two delay-el... | 08/07/2007 |
| 7221688 | Method and apparatus for receiving a digital audio broadcasting signal A method for processing a composite digital audio broadcasting signal including an analog modulated portion in a central frequency band and digitally modulated portions in upper and lower sidebands with respect to the central frequency band, the method comprises the... | 05/22/2007 |
| 7203718 | Apparatus and method for angle rotation An angle rotator uses a coarse stage rotation and a fine stage rotation to rotate an input complex signal in the complex plane according to an angle θ. The coarse stage rotation includes a memory device storing pre-computed cosine θM and sine θM | 04/10/2007 |
| 7190842 | Elementary cell of a linear filter for image processing The present invention relates to an elementary cell of a linear filter for image processing, as well as to a corresponding module, element and process. The cell comprises a data circulation output and a calculation output, as well as a main delay line and an auxilia... | 03/13/2007 |
| 7188135 | Analog adaptive FIR filter having independent coefficient sets for each filter tap A finite impulse response filter having tap weight rotation is provided, where each tap has a corresponding coefficient selector. Each coefficient selector includes N coefficients, where N is the number of taps. Each coefficient selector provides one of its correspo... | 03/06/2007 |
| 7184498 | Device and method for the digital demodulation of a signal received by selecting a filter and digital communication receiver comprising same The device (10) for digital demodulation comprises a polyphase filter (14) comprising a set of N distinct elementary digital filters and means (16) of selection, for each block of an elementary digital filter (Hi). It comprises... | 02/27/2007 |
| 7170957 | Device and method for the digital demodulation of a signal received by selecting a filter and digital communication receiver comprising same The device (10) for digital demodulation comprises a polyphase filter (14) comprising a set of N distinct elementary digital filters (Hi) and means (16) of selection, for each block of an elementary digital filter (Hi). The... | 01/30/2007 |
| 7162000 | Delay locked loop synthesizer with multiple outputs and digital modulation A delay locked loop circuit (200) in which multiple outputs are produced. A single delay line (24) is shared among multiple tap selection circuits (256A, 265B, 265C). Fixed phase shifts (412) can be introduced between multip... | 01/09/2007 |
| 7142010 | Programmable logic device including multipliers and configurations thereof to reduce resource utilization In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and ca... | 11/28/2006 |
| 7139341 | Receiver circuit for a communications terminal and method for processing signals in a receiver circuit A receiver circuit for a communications terminal includes a signal pre-processing circuit having: an analog/digital converter device with K analog/digital converters connected in parallel, a conversion device, and a filter device connected downstream of the conversi... | 11/21/2006 |
| 7110620 | Apparatus for processing digital image and method therefor An apparatus which processes a digital image and a method therefor which can reduce an error when calculating an output value obtained by interpolating pixel values of the input digital image. The apparatus includes an interpolation processing unit which interpolate... | 09/19/2006 |
| 7107301 | Method and apparatus for reducing latency in a digital signal processing device A digital signal processing device for processing an input signal includes delay generation circuitry and processing circuitry. The delay generation circuitry receives the input signal and includes a plurality of delay stages operatively coupled together, each of th... | 09/12/2006 |
| 7107302 | Finite impulse response filter algorithm for implementation on digital signal processor having dual execution units A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features... | 09/12/2006 |
| 7080108 | Discrete filter having a tap selection circuit A digital signal processing circuit includes a chain of processing units having a selectable number of taps and a tap selection circuit. The tap selection circuit is coupled to the chain of processing units to establish the number of taps of the chains. ... | 07/18/2006 |
| 7075363 | Tuned continuous time delay FIR equalizer An analog finite impulse response (“FIR”) filter generates a continuous time output using a chain of tunable delay elements. The tunable delay elements generate a time delay in an input signal. A calibration circuit, consisting of a control loop, tunes the delay... | 07/11/2006 |
| 7069212 | Audio decoding apparatus and method for band expansion with aliasing adjustment An audio decoding apparatus decodes high frequency component signals using a band expander that generates multiple high frequency subband signals from low frequency subband signals divided into multiple subbands and transmitted high frequency encoded information. Th... | 06/27/2006 |
| 7061975 | Noncyclic digital filter and radio reception apparatus comprising the filter In accordance with the invention, in a nonrecursive digital filter, the number of times each bit of input data passes through a shift register is reduced to save power. Despreading data is sent to a first shift register and a second shift register, each having a num... | 06/13/2006 |
| 7058119 | Parallel architecture digital filter and spread spectrum signal receiver using such a filter This invention relates to parallel architecture digital filter and signal receiver with spectrum spreading using such a filter, the filter may have p shift registers (Rp, Ri) with means for calculating a weighted sum of stored samples in the re... | 06/06/2006 |
| 7058571 | Audio decoding apparatus and method for band expansion with aliasing suppression A wideband, high quality audio signal is decoded with few calculations at a low bitrate. Unwanted spectrum components accompanying sinusoidal signal injection by a synthesis subband filter built with real-value operations are suppressed by inserting a suppression si... | 06/06/2006 |
| 7051059 | Oversampling FIR filter, method for controlling the same, semiconductor integrated circuit having the same, and communication system for transmitting data filtered by the same When changing the number of oversamples is performed, tap factors selected by selectors, which respectively correspond to holding parts in a shift register, are changed back to a predetermined number of tap factors used before the changing of the number of oversampl... | 05/23/2006 |
| 7047263 | Fast-settling digital filter and method for analog-to-digital converters A technique and circuit is provided for facilitating a faster settling time for a digital filter for use with an analog-to-digital converter. An exemplary technique utilizes a composite filter for a faster settling, lower noise resolution filter in a parallel config... | 05/16/2006 |
| 7046723 | Digital filter and method for performing a multiplication based on a look-up table A digital and a multiplication method are described, which lead to an efficient architecture for a hardware implementation of digital FIR and IIR filters into FPGAs. The multiplications of input sample data and delayed sample data with filter coefficients are perfor... | 05/16/2006 |
| 7042958 | Digital time alignment in a polar modulator Methods of and apparatus for digitally controlling, with sub-sample resolution, the relative timing of the magnitude and phase paths in a polar modulator. The timing resolution is limited by the dynamic range of the system as opposed to the sample rate. The methods ... | 05/09/2006 |
| 7024447 | Time continuous FIR filter to implement a hilbert transform and corresponding filtering method A finite impulse response (FIR) filter for implementing a Hilbert transform is provided. The FIR filter includes a plurality of programmable delay cells connected in cascade between an input terminal of the FIR filter and an output terminal of the FIR filter. Each p... | 04/04/2006 |
| 7016371 | Multi-mode adaptive filter A multi-mode device, capable of channel equalization and packet collision detection, includes a first switch, which is capable of receiving a transmit signal and a receive signal and outputting a filter input, which is multiplied by a first filter tap to generate a ... | 03/21/2006 |
| 7013319 | Digital filter methods and structures for increased processing rates Digital filters are provided that include a converter and a data processor. The converter converts successive strings of M successive data elements that occur at a system rate Fs in an input data stream Din to M parallel data elements that resp... | 03/14/2006 |
| 7007053 | Area efficient realization of coefficient architecture for bit-serial FIR, IIR filters and combinational/sequential logic structure with zero latency clock output An area-efficient realization of a coefficient block includes hardware sharing techniques and optimizations applied to this block. The block is connected to coefficient lines coming from a delay block to be connected to perform a filtering operation or a mathematica... | 02/28/2006 |
| 6996593 | Filter processing apparatus and its control method, program, and storage medium This invention has as its object to suppress an increase in circuit scale and to simplify a circuit structure by executing a filter process using a plurality of arithmetic units each of which makes multiplication and addition. To achieve this object, image data Yn+2... | 02/07/2006 |
| 6980592 | Digital adaptive equalizer for T1/E1 long haul transceiver The present invention relates to the implementation of a digital adaptive equalizer for a T1/E1 long haul transceiver which is capable of adapting to a wide range of cable types, cable lengths, and/or other data transmission impairments, particularly when the transm... | 12/27/2005 |
| 6970897 | Self-timed transmission system and method for processing multiple data sets A self-timed transmission system and method are disclosed. An encoder encodes first and second data operands that are each defined on separate respective first and second sets of logic paths onto the same third set of logic paths by changing the encoding scheme. The... | 11/29/2005 |
| 6968296 | Cable detector with decimating filter and filtering method A cable detection or location device is disclosed having a detection stage to produce a detection signal, a decimating filter having an input and an output, the input being coupled to the receiving stage to filter the detection signal and output a down-sampled filte... | 11/22/2005 |
