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The Quarterly Review ; March edition, 1825
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| Number | Title | Issue Date |
| 8099448 | Arithmetic logic and shifting device for use in a processor An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectiv... | 01/17/2012 |
| 8069195 | Method and system for a wiring-efficient permute unit A method of providing wiring efficiency in a permute unit. Multiple selectors receive input data and shared control signals from multiple register files. The permute unit includes multiple multiplexors (MUXs) coupled to multiple logical AND gates. The multiple logic... | 11/29/2011 |
| 8055695 | Shift register with each stage controlled by a specific voltage of the next stage and the stage after thereof A shift register has shift register units. The nth shift register unit includes first to third level control units and first and second driving units. The first and second level control units respectively provide a first clock signal and a first voltage t... | 11/08/2011 |
| 8046396 | Residual Fourier-padding interpolation for instrumentation and measurement A technique for interpolating a series of samples includes constructing a mathematical model of the series that describes its large signal behavior. The model is subtracted from the original series to yield a residue. A discrete Fourier transform (DFT) is taken of t... | 10/25/2011 |
| 8041755 | Fast static rotator/shifter with non two's complemented decode and fast mask generation In one embodiment, a rotator, a mask generator, and circuitry configured to mask the rotated operand output by the rotator with the output mask generated by the mask generator perform a shift operation. The rotator is configured to rotate the input operand by the sh... | 10/18/2011 |
| 7949697 | Bit field operation circuit A bit field operation circuit has a first shift unit, a mask shift amount control circuit, a second shift unit, a logic operation unit, and a selection unit. The first shift unit outputs a first intermediate data based on a first control signal. The mask shift amoun... | 05/24/2011 |
| 7860911 | Extended precision accumulator A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move the contents of a portion of the extended accumulator to a general-p... | 12/28/2010 |
| 7818356 | Bitstream buffer manipulation with a SIMD merge instruction Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is ... | 10/19/2010 |
| 7783692 | Fast flag generation A method and circuit for fast flag generation. The circuit is coupled to receive data to be shifted, the data including a first plurality of bits. A shift count value (including a second plurality of bits) is also received by the circuit, as well as an indication of... | 08/24/2010 |
| 7716264 | Method and apparatus for performing alignment shifting in a floating-point unit An apparatus for performing alignment shifting in a floating-point unit is disclosed. An alignment shifter includes a shift amount calculator, a set of first level shifters and a set of second level shifter. The shift amount calculator generates one shift amount und... | 05/11/2010 |
| 7689635 | Area efficient shift / rotate system An area efficient data shifter/rotator using a barrel shifter. The invention is a circuit, which uses a single barrel shifter and is controllable to implement either a left or right shift or rotation of bits of a digital data word. The circuit is dynamically control... | 03/30/2010 |
| 7650373 | Source driver with multi-channel shift register A source driver for use in a display device having a shift register unit for sequentially activating output signals. The shift register unit includes a plurality of shift registers connected in series, wherein Nth shift register among the plurality of shift register... | 01/19/2010 |
| 7631025 | Method and apparatus for rearranging data between multiple registers Method, apparatus, and program means for rearranging data between multiple registers. The method of one embodiment comprises shuffling first set of packed data from a first source based on a first set of masks to produce a first set of shuffled data. The first set o... | 12/08/2009 |
| 7606848 | Detector in parallel with a logic component One or more detectors are provided for processing input in parallel with a logic component receiving the same input. Apparatus described herein include one or more logic components that are configured to perform logical operations on an input vector, and one or more... | 10/20/2009 |
| 7543007 | Residue-based error detection for a shift operation Errors in a shift result can be detected with a residue-based mechanism, instead of with duplication of an entire shifter. The commutative property of residue computation over a bit string allows the residue of a value to be independent of the actual bit positions w... | 06/02/2009 |
| 7539715 | Method and system for saturating a left shift result using a standard shifter A method for left shifting data includes left shifting the data to produce a left-shift result, right shifting the data to produce a right-shift result, and determining if the left-shift result requires saturation based on the right-shift result. ... | 05/26/2009 |
| 7480686 | Method and apparatus for executing packed shift operations A method and apparatus for performing a shift operation on packed data elements having multiple values. One embodiment includes accessing the shift control signal of a first format from a memory. The shift control signal identifyies a first packed shift operation an... | 01/20/2009 |
| 7461109 | Method and apparatus for providing packed shift operations in a processor A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. One embodiment of a central processing unit (CPU) includes instruction fetch logic to fetch a single-instruction-multiple-data (SIMD) shift instr... | 12/02/2008 |
| 7461108 | Barrel shift device When a barrel shift device is divided into pipeline registers and a shift process is executed in a multistage process stage, by decoding a second control signal for controlling a shift amount of a second shift circuit 50 using a decoding circuit 20, it... | 12/02/2008 |
| 7451169 | Method and apparatus for providing packed shift operations in a processor A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the m... | 11/11/2008 |
| 7409415 | Processor system with efficient shift operations including EXTRACT operation An electronic system (2001) for manipulating an input data argument (D[31:0]) comprising an integer number of bits. The system comprises an input (R) for receiving a right direction argument and an input (L) for receiving a left direction argument.... | 08/05/2008 |
| 7392270 | Apparatus and method for reducing the latency of sum-addressed shifters The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a b... | 06/24/2008 |
| 7349934 | Processor system and method with combined data left and right shift operation An integrated circuit device (100) includes circuitry for providing a first shift argument (L[4:0]) indicating shift positions in a first direction and circuitry for providing a second shift argument (R[4:0]) indicating shift positions in a second direction. ... | 03/25/2008 |
| 7350058 | Shift and insert instruction for overwriting a subset of data within a register with a shifted result of another register A data processing system 2 is provided which supports shift-and-insert instructions SLI, SRI which serve to shift a source data value by a specified shift amount and then insert bits from that shifted value other than the shifted-in bits into a destination va... | 03/25/2008 |
| 7343388 | Implementing crossbars and barrel shifters using multiplier-accumulator blocks An interface receiver, which is part of an interface that allows the transfer of data between two incompatible I/O standards, includes a crossbar and a barrel shifter that can be implemented using multiplier-accumulator blocks. The crossbar reorders an incoming burs... | 03/11/2008 |
| 7340495 | Superior misaligned memory load and copy using merge hardware Method, apparatus, and program means for performing misaligned memory load and copy using aligned memory operations together with a SIMD merge instruction. The method of one embodiment comprises determining whether a memory operation involves a misaligned memory add... | 03/04/2008 |
| 7337202 | Shift-and-negate unit within a fused multiply-adder circuit A low-power shift-and-negate unit within a fused multiply-adder circuit is disclosed. The shift-and-negate unit includes a large shift stage, a coarse shift stage, a negate stage and a fine shift stage. The large shift stage receives a first set of shift signals and... | 02/26/2008 |
| 7320013 | Method and apparatus for aligning operands for a processor A method for transparently presenting different size operands to be processed is provided. The method initiates with providing a first operand having a first bit-width. Then, a bit width of a second operand associated with a processor is determined. The second opera... | 01/15/2008 |
| 7296049 | Fast multiplication circuits Fast multiplication of two operands may be achieved by an interstitial product generator that generates an interstitial product from each of a plurality of mult-ibit segments of a multiplier. Generation of a final product is made faster because fewer interstitial pr... | 11/13/2007 |
| 7278138 | Computer program conversion and compilation The present invention provides methods, apparatus, and systems to remove a redundant, sign extension instruction from a program and to improve the execution efficiency of the program. In an example embodiment, a conversion program for controlling a computer for the ... | 10/02/2007 |
| 7272622 | Method and apparatus for parallel shift right merge of data A method for a parallel shift right merge of data. The method of one embodiment comprises receiving a shift count of M. A first operand having a first set of L data elements is shifted left by ‘L−M’ data elements. A second operand having a second set of L data... | 09/18/2007 |
| 7272624 | Fused booth encoder multiplexer A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results... | 09/18/2007 |
| 7254699 | Aligning load/store data using rotate, mask, zero/sign-extend and or operation The present invention relates generally to microprocessor or microcontroller architecture, and particularly to an architecture structured to handle unaligned memory references. A method is disclosed for loading unaligned data stored in several memory locations, incl... | 08/07/2007 |
| 7251248 | Connection device A connection device comprises a first physical device, a first device driver layer, a first interface abstraction layer, in which is embedded a first software support layer, a data core, a second interface abstraction layer, in which is embedded a second software su... | 07/31/2007 |
| 7251759 | Method and apparatus to compare pointers associated with asynchronous clock domains A multi-bit write pointer that is associated with a first clock can be converted to a single-bit write pointer. A multi-bit read pointer that is associated with a second clock can be converted to a single-bit read pointer. The first clock and the second clock are no... | 07/31/2007 |
| 7231561 | Apparatus and method for data pattern alignment A digital tester includes a digital data pattern aligner. The digital data pattern aligner includes an alignment pattern source, a data shifter, and a data comparator. The alignment pattern source sends an alignment pattern to the comparator in a data stream. The co... | 06/12/2007 |
| 7225212 | Extended precision accumulator A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move the contents of a portion of the extended accumulator to a general-p... | 05/29/2007 |
| 7213129 | Method and system for a two stage pipelined instruction decode and alignment using previous instruction length A system and method for aligning an instruction stream is described. The system comprises a rotator logic unit for rotating data bytes of the instruction stream. A shifter logic unit is used for shifting the data bytes to the start of a instruction based upon a leng... | 05/01/2007 |
| 7210023 | Data processing apparatus and method for moving data between registers and memory in response to an access instruction having an alignment specifier identifying an alignment to be associated with a start address The present invention provides a data processing apparatus and method for performing aligned access operations. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements, and a processor operable to... | 04/24/2007 |
| 7206800 | Overflow detection and clamping with parallel operand processing for fixed-point multipliers A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The invention predicts when a multiplication of a number of operands will exceed a pre-determined number of bits based upon the fixe... | 04/17/2007 |
