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| Number | Title | Issue Date |
| 7337154 | Method for solving the binary minimization problem and a variant thereof A recursive binary splitting and recombination procedure coupled with a specially tailored genetic algorithm provides a solution to the general binary minimization problem with much lower run times than other methods. A minor modification to the procedure solves a v... | 02/26/2008 |
| 7024636 | Chip management system A method and system for automatically guiding a user through a design flow for an integrated circuit are disclosed. The method and system include displaying a design flow user interface on a user's computer, where the user interface includes symbols corresponding to... | 04/04/2006 |
| 7020852 | Automation of the development, testing, and release of a flow framework and methodology to design integrated circuits An automated framework and methodology for the development, testing, validation, and documentation of the design of semiconductor products that culminates in the release of a design kit having a flow manager and flow file to actualize a methodology to design a semic... | 03/28/2006 |
| 6993538 | System and process for identifying objects and/or points nearby a given object or point A system and process is presented that identifies nearby objects and/or points in relation to a base object or point. An object or point is nearby if it resides within a prescribed area around the base point. The identification is based on information accessed from ... | 01/31/2006 |
| 6968517 | Method of interactive optimization in circuit design A method of interactively determining at least one optimized design candidate using an optimizer, the optimizer having a generation algorithm and an objective function, the optimized design candidate satisfying a design problem definition, comprises generating desig... | 11/22/2005 |
| 6751735 | Apparatus for control of cryptography implementations in third party applications An apparatus and method provide a controlled, dynamically loaded, modular, cryptographic implementation for integration of flexible policy implementations on policy engines, and the like, into a base executable having at least one slot. The base executable may rely ... | 06/15/2004 |
| 6424959 | Method and apparatus for automatic synthesis, placement and routing of complex structures The present invention consists of a method and apparatus for the automatic creation of the topology, component sizing, placement, and routing of complex structures, such as electronic circuits or mechanical systems, to satisfy prespecified high-level desi... | 07/23/2002 |
| 6292766 | Simulation tool input file generator for interface circuitry The present invention is a simulation tool input file generator implemented in a computer system that permits a designer to efficiently and effectively create and modify electrical circuit simulation tool input files. The simulation tool input file genera... | 09/18/2001 |
| 6283759 | System for demonstrating compliance with standards Compliance with a standard is demonstrated by displaying a floor plan on a first computer. The displayed floor plan includes designated areas. Each designated area includes a corresponding communication link, and the designated areas are regulated by the ... | 09/04/2001 |
| 5892678 | LSI design automation system An improved LSI design automation system includes: an input unit, a circuit component storage unit, a circuit component selection unit, a design method decision unit, a design process unit, and a component entry unit. The input unit receives LSI function ... | 04/06/1999 |
| 5856925 | Method for making electronic circuit design data and CAD system using the method In a method for managing design data regarding an electronic circuit in order to design and analyze the electronic circuit, the design data is arranged according to a hierarchical-layer module structure. The design data in each of hierarchical layers of t... | 01/05/1999 |
| 5812740 | Advanced modular cell placement system with neighborhood system driven optimization A system for computing an affinity for relocating a cell on a surface of a semiconductor chip is disclosed herein. The cell is located within a region and belongs to a net of cells. The system initially computes a weight associated with all cells in the n... | 09/22/1998 |
| 5768161 | Data processing apparatus A data processing apparatus includes apparatus for modelling asynchronous logic circuits as at least two of circuit elements the functions of which are governed by a set of rules each defining a response to a given condition. For elements functioning as r... | 06/16/1998 |
| 5761080 | Method and apparatus for modeling capacitance in an integrated circuit According to the present embodiment, a method for calculating the parasitic capacitance in a semiconductor device is disclosed. According to the preferred method, a layout file containing the shapes of a semiconductor device is provided. The dimensions of... | 06/02/1998 |
| 5748844 | Graph partitioning system A system is disclosed for computing an initial partition of a graph comprising nodes and the edges that connect the nodes. In one embodiment this initial partition is presented for subsequent use by the Kernighan-Lin system of graph partitioning. The Subj... | 05/05/1998 |
| 5734798 | Method and apparatus for extracting a gate modeled circuit from a fet modeled circuit A method of extracting a gate model from a fet model using a computer implemented expert system apparatus to perform the steps of recognizing power, ground and clock signals; recognizing inverters; recognizing and preserving all logic signals of the fet m... | 03/31/1998 |
| 5734572 | Tool which automatically produces an abstract specification of a physical system and a process for producing a physical system using such a tool A tool for verifying a process for producing a physical system by automatically deducing the functional description of the system produced. From the concrete description GND which contains the elements of a physical system and the connections between thes... | 03/31/1998 |
| 5640497 | Layout redesign using polygon manipulation A method and system for redesigning layouts adjusts polygon data to develop a new layout which meets new design rules. Polygon data defining the original layout is further broken down into equated layers which are logical combinations of the layers in the... | 06/17/1997 |
| 5592392 | Integrated circuit design apparatus with extensible circuit elements Method and apparatus for design integrated circuit layouts with extensible elements. The elements are generated by extensible element programs the first time the element is selected for a design, with the results stored in a run time cache. Element entrie... | 01/07/1997 |
| 5572710 | High speed logic simulation system using time division emulation suitable for large scale logic circuits A logic simulation system capable of handling a very large scale circuit while realizing a high speed simulation by retaining the parallelism of the simulation targets. The system includes: a host computer having data of the simulation target divided into... | 11/05/1996 |
| 5563993 | Logic simulator system using both free-format display format and stream display format In a logic simulation system, a first management table manages time-series data of signal values for each signal terminal, constituting logic simulation result information. A setting unit sets one or a plurality of display formats for logic simulation res... | 10/08/1996 |
| 5557537 | Method and apparatus for designing and editing a distribution system for a building A method and apparatus for designing and editing a distribution system for a building is disclosed. Elements of such distribution systems and requirements of relevant standard, are stored in a computer's memory. Building parameters are entered into a comp... | 09/17/1996 |
| 5553274 | Vertex minimization in a smart optical proximity correction system An optical proximity correction (OPC) routine that enhances the fidelity of VLSI pattern transfer operations such as photolithography and reactive ion etch (RIE) by predistorting the mask while biasing only critical features and eliminating, as much as po... | 09/03/1996 |
| 5553273 | Vertex minimization in a smart optical proximity correction system An optical proximity correction (OPC) routine that enhances the fidelity of VLSI pattern transfer operations such as photolithography and reactive ion etch (RIE) by predistorting the mask while biasing only critical features and eliminating, as much as po... | 09/03/1996 |
| 5550839 | Mask-programmed integrated circuits having timing and logic compatibility to user-configured logic arrays Method and apparatus for producing mask-configured integrated circuits which are pin, logic, and timing compatible substitutes for user-configured logic arrays, without the need for logic or timing simulations of the mask-configured circuit design. Scan t... | 08/27/1996 |
| 5546321 | Method and apparatus for the cross-sectional design of multi-layer printed circuit boards Disclosed is a design tool and a method of fabricating a multi-layer printed circuit board. The method utilizes the design tool. The knowledge base means has both (1) printed circuit board cross sectional geometric parameter to transmission line parameter... | 08/13/1996 |
| 5535134 | Object placement aid An existing layout is modified to ensure compliance with design rules and any user-defined rules by deriving a horizontal constraint model and a vertical constraint model. For each of the vertical and horizontal orientations in turn, violations of the rul... | 07/09/1996 |
| 5519633 | Method and apparatus for the cross-sectional design of multi-layer printed circuit boards Disclosed is a design tool and a method of fabricating a multi-layer printed circuit board. The method utilizes the design tool. The knowledge base means has both (1) printed circuit board cross sectional geometric parameter to transmission line parameter... | 05/21/1996 |
| 5517428 | Optimizing a piping system This invention relates to a structural optimization method, specifically to an optimization method that will minimize the weight of a piping system and satisfy the design constraints. This invention utilizes the information generated by a computer-aided d... | 05/14/1996 |
| 5490232 | Computer-aided thought process simulation design system A computer-aided design system simulates the designer thought processes by the provision of a plurality of discrete unit programs provided respectively for individual design items, Each of the unit programs includes a thought process portion, a knowledge ... | 02/06/1996 |
| 5452224 | Method of computing multi-conductor parasitic capacitances for VLSI circuits A method of computing parasitic capacitances between multiple electrical conductors within an electric circuit computes a division of the circuit's physical layout into a plurality of windows. The parasitic capacitances associated with the conductors of e... | 09/19/1995 |
| 5416718 | Circuit design support system and circuit producing method In a circuit design support system, a logic minimizing unit receives data indicating a functional specification of a desired circuit and minimizes logical sequences of the desired circuit. A cell assignment unit assigns cells to each of minimized logical ... | 05/16/1995 |
| 5353401 | Automatic interface layout generator for database systems An automatic interface layout generator for database systems is disclosed herein. The automatic generator includes a specification tool for specifying a set of block descriptions representative of specified portions of a database. A block layout generator... | 10/04/1994 |
| 5329464 | Utility layout design system A method of designing a utility distribution system. The method begins with lot data that geographically defines lots in an area to which the utility will be provided. The lot data is stored in a computer in a geographic information system (GIS). The lot ... | 07/12/1994 |
| 5311443 | Rule based floorplanner A rule based floorplanner for a macrocell array having a plurality of predetermined macrocells. The floorplanner uses a net list (23), a macrocell list (26), and a list of design constraints (31) and characteristics of the base array itself to derive an i... | 05/10/1994 |
| 5267146 | System for designing configuration with design elements characterized by fuzzy sets A system for designing a configuration capable of accounting for subtle variations of each design element involved. In this system, evaluation terms which expresses impressions associated with the design elements of the configuration is entered; a fuzzy k... | 11/30/1993 |
| 5228117 | Expert system development support system and expert system environment utilizing a frame processing technique An expert system in which a plurality of knowledge descriptive layers are provided in a frame system. Each descriptive layer is composed of several frames. The frames of the lower knowledge descriptive layer correspond to the elements of a knowledge proce... | 07/13/1993 |
| 5225987 | System for implementing a PC computer configuration system for assembling and mounting of a complex product in situ A generic tool is provided by storing into a PC computer data representing structurally a vertical section and objects to be placed inside the vertical section, and by manipulating virtually with the PC computer selected objects in relation to cases withi... | 07/06/1993 |
| 5212650 | Procedure and data structure for synthesis and transformation of logic circuit designs A procedure is described for the synthesis and transformation of a logic circuit design, provided by the designers, into a database capable of being used to fabricate the actual circuit. The procedure involves the use of model instances which represent th... | 05/18/1993 |
| 5204939 | Rule base processing system and rule evaluation control method therein A rule base processing system for processing rules with an inference engine is provided with a control block and a number of knowledge source blocks containing the rules. The control block contains a knowledge source list of the knowledge source blocks an... | 04/20/1993 |
