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| Number | Title | Issue Date |
| 7272585 | Operation circuit and operation control method thereof A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascendin... | 09/18/2007 |
| 7254565 | Method and circuits to virtually increase the number of prototypes in artificial neural networks An improved Artificial Neural Network (ANN) is disclosed that comprises a conventional ANN, a database block, and a compare and update circuit. The conventional ANN is formed by a plurality of neurons, each neuron having a prototype memory dedicated to store a proto... | 08/07/2007 |
| 7120291 | Method and apparatus for analyzing input information A method and an apparatus operate like a human neural network to analyze and store input information and form patterns according to the input and stored information. The apparatus has a preprocessing unit (3), an activity computation unit (5), a mutual... | 10/10/2006 |
| 7120617 | Operation circuit and operation control method thereof A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascendin... | 10/10/2006 |
| 7092921 | Artificial associative neuron synapse The invention relates to a method for determining a weight coefficient of an artificial associative neuron synapse, where the synaptic weight coefficient is determined on the basis of the temporal average of a product of two signals. The method comprises the steps o... | 08/15/2006 |
| 7085749 | Pulse signal circuit, parallel processing circuit, pattern recognition system, and image input system A synaptic connection element for connecting neuron elements inputs a plurality of pulsed signals from different neuron elements N1 through N4, effects a common modulation (time window integration or pulse phase/width modulation) on a plurality of pred... | 08/01/2006 |
| 7082419 | Neural processing element for use in a neural network A neural processing element for use in a modular neural network is provided. One embodiment provides a neural network comprising an array of autonomous modules (300). The modules (300) can be arranged in a variety of configurations to form neural netwo... | 07/25/2006 |
| 7065688 | Simultaneous multiprocessor memory testing and initialization In a system having a plurality of processing nodes, wherein each of the plurality of processing nodes has an assigned portion of system memory such that the assigned portion of system memory of each of the plurality of processing nodes is accessible by the plurality... | 06/20/2006 |
| 7058790 | Cascaded event detection modules for generating combined events interrupt for processor action An eventpoint chaining apparatus for generalized event detection and action specification in a processing environment is described. In one aspect, the eventpoint chaining apparatus includes a first processor which has a programmable eventpoint module with an input t... | 06/06/2006 |
| 7028250 | System and method for automatically classifying text A method is provided for automatically classifying text into categories. In operation, a plurality of tokens or features are manually or automatically associated with each category. A weight is then coupled to each feature, wherein the weight indicates a degree of a... | 04/11/2006 |
| 6959376 | Integrated circuit containing multiple digital signal processors The present invention is an integrated circuit containing multiple digital signal processors (DSPs). A single host processor interface is also placed on the chip to connect the multiple DSPs to the host. A separate direct memory access (DMA) unit is provided for eac... | 10/25/2005 |
| 6873994 | Conflict detection and resolution in association with data allocation A method for detecting and resolving conflicts in association with a data allocation includes determining a relationship between each of a plurality of positions in a hierarchical organization of data. The method also includes selecting a position i and determining ... | 03/29/2005 |
| 6801655 | Spatial image processor A spatial image processor neural network for processing image data to discriminate between first and second spatial configurations of component objects includes a photo transducer input array for converting an input image to pixel data and sending the data to a loca... | 10/05/2004 |
| 6535862 | Method and circuit for performing the integrity diagnostic of an artificial neural network A diagnostic method engages all the neurons of an artificial neural network (ANN) based on mapping an input space defined by vector components based on category, context, and actual field of influence (AIF). The method includes the steps loading the compo... | 03/18/2003 |
| 6519577 | Digital signal filter using weightless neural techniques A number of consecutive samples in unit distance code (here Gray code) are effectively stacked and supplied to respective sum and threshold devices 20 corresponding to each bit position, to determine the bulk property or "generic result" of the consecutiv... | 02/11/2003 |
| 6502083 | Neuron architecture having a dual structure and neural networks incorporating the same The improved neuron is connected to input buses which transport input data and control signals. It basically consists of a computation block, a register block, an evaluation block and a daisy chain block. All these blocks, except the computation block sub... | 12/31/2002 |
| 6456992 | Semiconductor arithmetic circuit A semiconductor arithmetic circuit which compares the magnitudes of a plurality of data with each other in real time by using a simple circuit. The semiconductor arithmetic circuit containing one or more neuron MOS transistors each having a plurality of input ... | 09/24/2002 |
| 6405184 | Process for producing fault classification signals A method for generating fault classification signals which identify faulty loops which develop in a multiphase energy supply network observed in the event of a fault from a protective device with a starting arrangement. To be able to generate such fault c... | 06/11/2002 |
| 6405185 | Massively parallel array processor Image processing for multimedia workstations is a computationally intensive task requiring special purpose hardware to meet the high speed requirements associated with the task. One type of specialized hardware that meets the computation high speed requir... | 06/11/2002 |
| 6397201 | E-cell (equivalent cell) and the basic circuit modules of e-circuits: e-cell pair totem, the basic memory circuit and association extension The e-cell is a computational element for the construction of circuits capable of performing transform invariant pattern recognition, scene segmentation, and regularity extraction in a variety of sensory modes including vision, hearing, olefaction, touch,... | 05/28/2002 |
| 6338052 | Method for optimizing matching network of semiconductor process apparatus A method for optimizing matching network between an output impedance and an input impedance in a semiconductor process apparatus is disclosed. The method includes the steps of: providing a neural network capable of being trained through repeated learning;... | 01/08/2002 |
| 6115712 | Mechanism for combining data analysis algorithms with databases on the internet An open architecture for arbitrarily combining data analysis algorithms and databases on the Internet where the data analysis algorithm and database may be from different vendors or suppliers. At the request of a customer, the two are combined on the fly ... | 09/05/2000 |
| 6078190 | Threshold logic with improved signal-to-noise ratio The threshold value logic has a non-inverting circuit path (S) that and an inverting circuit path (S') are connected to at least one comparative weighting subcircuit (BC, BS). The non-inverting circuit path and the inverting circuit path preferably are of... | 06/20/2000 |
| 6041299 | Apparatus for calculating a posterior probability of phoneme symbol, and speech recognition apparatus There are disclosed an apparatus for calculating a posteriori probabilities of phoneme symbols and a speech recognition apparatus using the apparatus for calculating a posteriori probabilities of phoneme symbols. A feature extracting section extracts spee... | 03/21/2000 |
| 5995669 | Image processing method and apparatus An image processing apparatus includes an input unit for entering a plurality of color image signals, an image processing unit for subjecting the plurality of entered color image signals to processing based upon an algorithm of a cellular neural network, ... | 11/30/1999 |
| 5835682 | Dynamical system analyzer A dynamical system analyser (10) incorporates a computer (22) to perform a singular value decomposition of a time series of signals from a nonlinear (possibly chaotic) dynamical system (14). Relatively low-noise singular vectors from the decomposition are... | 11/10/1998 |
| 5768476 | Parallel multi-value neural networks In a parallel multi-value neural network having a main neural network 16 and a sub neural network 18 coupled with the main neural network 16 in parallel for an input signal, the main neural network 16 is trained with a training input signal by using a mai... | 06/16/1998 |
| 5764856 | Parallel neural networks having one neural network providing evaluated data to another neural network A data processing system is provided that consists of a connection of a first neural network (N1) with at least one other neural network (N21, N22, . . . , N2n). The first neural network (N1) and the ... | 06/09/1998 |
| 5748849 | Neural processor comprising distributed synaptic cells A neural net has a physical topology independent of its functional topology. Cells, being functional equivalents of synapses, are concatenated to form a unidirectional data path. The cells are connected in parallel to a bus for individual or parallel cont... | 05/05/1998 |
| 5640586 | Scalable parallel group partitioned diagonal-fold switching tree computing apparatus A parallel computer architecture supporting neural networks utilizing a novel method of separating a triangular array containing N processing elements on each edge into multiple smaller triangular arrays, each of dimension X and each representing a common... | 06/17/1997 |
| 5608844 | Neural processor comprising distributed synaptic cells The neural net has a physical topology independent of its functional topology. Cells, being functional equivalents of synapses, are concatenated to form a unidirectional data path. The cells are connected in parallel to a bus for individual or parallel co... | 03/04/1997 |
| 5604840 | Information processing apparatus An information processing apparatus is composed of an input layer, a hidden layer and an output layer, and performs a computation in terms of neuron models. In the information processing apparatus, a forward network comprising the input layer, the hidden ... | 02/18/1997 |
| 5600843 | Ring systolic array system for synchronously performing matrix/neuron computation using data transferred through cyclic shift register connected in cascade of trays A parallel data processing system comprises a plurality of data processing units each having at least one input and storing data of a matrix and a plurality of trays each having a first input and an output and for storing data of a vector, each of all or ... | 02/04/1997 |
| 5530953 | Apparatus for relocating spatial information for use in data exchange in a parallel processing environment The apparatus includes a plurality of groups of plural data paths which are connected in such a manner that each data path of one group intersects with one or more data paths of another or more data path groups. Each data path of each group is composed of... | 06/25/1996 |
| 5530886 | Object recognition apparatus using a hierarchical network of recognition units A recognizing and judging apparatus for a learning and recognizing processing to be effectively performed in a short period of time, the apparatus including a plurality of recognition units in a multi-layered hierarchical network structure with one or mor... | 06/25/1996 |
| 5517596 | Learning machine synapse processor system apparatus A Neural synapse processor apparatus having a neuron architecture for the synapse processing elements of the apparatus. The apparatus which we prefer will have a N neuron structure having synapse processing units that contain instruction and data storage ... | 05/14/1996 |
| 5471627 | Systolic array image processing system and method A systolic array of processing elements is connected to receive weight inputs and multiplexed data inputs for operation in two dimension convolution mode, or fully-connected neural network mode, or in cooperative, competitive neural network mode. Feature ... | 11/28/1995 |
| 5422983 | Neural engine for emulating a neural network The neural engine (20) is a hardware implementation of a neural network for use in real-time systems. The neural engine (20) includes a control circuit (26) and one or more multiply/accumulate circuits (28). Each multiply/accumulate circuit (28) includes ... | 06/06/1995 |
| 5337395 | SPIN: a sequential pipeline neurocomputer A neural network architecture consisting of input weight multiplications, product summation, neural state calculations, and complete connectivity among the neuron processing elements. Neural networks are modelled using a sequential pipelined neurocomputer... | 08/09/1994 |
| 5329611 | Scalable flow virtual learning neurocomputer A scalable flow virtual learning neurocomputer system and appratus with a scalable hybrid control flow/data flow employing a group partitioning algorithm, and a scalable virtual learning architecture, synapse processor architecture mapping, inner square f... | 07/12/1994 |
