Bizarre Patents
Method and apparatus for making a drink hop along a bar or counter
A method for generating a drink which appears to hop from a remote spot on the bar or counter and take one or more leaps, before landing in a patron's glass.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8112265 | Simulating loss of logic power state due to processor power conservation state In general, in one aspect, the disclosure describes creation of a randomization list that includes only a subset of the logic states of an integrated circuit (IC). The subset being selectable by signal so as to define logic states that can be randomized for specific... | 02/07/2012 |
| 8108816 | Device history based delay variation adjustment during static timing analysis A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a... | 01/31/2012 |
| 8108815 | Order independent method of performing statistical N-way maximum/minimum operation for non-Gaussian and non-linear distributions A method and system to improve the performance of an integrated circuit (IC) chip by removing timing violations detected by performing a statistical timing analysis, given distributions of process and environmental sources of variation. The distributions are quantiz... | 01/31/2012 |
| 8108819 | Object placement in integrated circuit design A method, system, and computer usable program product for an improved object placement in integrated circuit design are provided in the illustrative embodiments. The IC design includes cells, the cells including electronic components, wires, and pins defined for int... | 01/31/2012 |
| 8091051 | Behavioral synthesis apparatus, method, and program having test bench generation function Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation mea... | 01/03/2012 |
| 8082527 | Representing the behaviors of a packet processor Methods are provided for compactly representing behaviors of a processor of packets. A declarative description of the processor is input. The declarative description specifies rules for manipulating the packets. A dependency graph is generated from the declarative d... | 12/20/2011 |
| 8079004 | Efficient exhaustive path-based static timing analysis using a fast estimation technique One embodiment of the present invention provides a system that performs an efficient path-based static timing analysis (STA) in a circuit design. During operation, the system identifies a set of paths within the circuit design, wherein each path includes one or more... | 12/13/2011 |
| 8074192 | Verification support apparatus, verification support method, and computer product The circuit volume of a system under design is reduced by a circuit conversion involving consolidation (sharing) of common parts in the system by a representative part. The design data of the system post-conversion is used to verify operation of the system. However,... | 12/06/2011 |
| 8050904 | System and method for circuit symbolic timing analysis of circuit designs A method, data processing system, and computer program product are provided for performing time-based symbolic simulation. A delay-aware representation of a circuit is created that includes a plurality of circuit nodes. The data-aware representation is simulated. In... | 11/01/2011 |
| 8042085 | Method for compaction of timing exception paths A technique and apparatus for reducing the complexity of optimizing the performance of a designed semiconductor circuit is disclosed. This technique of path compaction is used to reduce the time taken for optimization. The path compaction tool is used in design opti... | 10/18/2011 |
| 8037438 | Techniques for parallel buffer insertion The present disclosure is directed to a method for determining a plurality of buffer insertion locations in a net for an integrated circuit design. The method may comprise calculating a plurality of resistive-capacitive (RC) influences in parallel, each RC influence... | 10/11/2011 |
| 8028259 | Automated method and apparatus for very early validation of chip power distribution networks in semiconductor chip designs Validation of full-chip power distribution networks can be performed very early, and continuously throughout the design cycle, to detect real physical power connection problems and enable early correction of power grid designs using early floor plan and power grid d... | 09/27/2011 |
| 8020123 | Transaction-based system and method for abstraction of hardware designs Apparatus and method for transaction-based abstraction process can, in an embodiment, include three main phases: first, selecting a set of transaction-processing finite state machines (FSMs) that determine transaction boundaries. Second, extracting the transaction-p... | 09/13/2011 |
| 8020129 | Multiple voltage threshold timing analysis for a digital integrated circuit An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digita... | 09/13/2011 |
| 8010921 | System and method for statistical timing analysis of digital circuits The present invention is a system and method for statistical or probabilistic static timing analysis of digital circuits, taking into account statistical delay variations. The delay of each gate or wire is assumed to consist of a nominal portion, a correlated random... | 08/30/2011 |
| 7987086 | Software entity for the creation of a hybrid cycle simulation model Disclosed is a software entity for constructing a Hybrid Cycle Simulation model comprising Compiled Data Units (CDUs) for use in design verification. The simulation model may contain a plurality of 1-cycle CDUs, optimized for simulation throughput, and 2-cycle CDUs,... | 07/26/2011 |
| 7979819 | Minterm tracing and reporting Disclosed are a method, a system and a computer program product for determining and reporting minterms to aid in implementing an engineering change order (ECO). A Minterm Tracing and Reporting (MTR) utility, which executes on a computer system, receives two or more ... | 07/12/2011 |
| 7975249 | Operation timing verifying apparatus and program An operation timing verifying apparatus and program for accurately verifying operation timings of a semiconductor integrated circuit in design with suppressing design time and cost. The operation timing verifying apparatus and program sets an unreal corner condition... | 07/05/2011 |
| 7971166 | Method, system, and program product for automated verification of gating logic using formal verification Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testb... | 06/28/2011 |
| 7962874 | Method and system for evaluating timing in an integrated circuit Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and lat... | 06/14/2011 |
| 7949510 | Distributed simultaneous simulation A method and system for distributed simultaneous simulation are provided, the method including providing a state of at least one storage unit, providing a segment of the circuit bounded by the at least one storage unit, and simulating the segment in accordance with ... | 05/24/2011 |
| 7941774 | Partial timing modeling for gate level simulation Various apparatuses, methods and systems for creating an integrated circuit and performing a gate level simulation of a circuit are disclosed herein. For example, some embodiments of the present invention provide a system for performing a gate level simulation of a ... | 05/10/2011 |
| 7934190 | Multiple amplifier matching over lumped networks of arbitrary topology A method includes generating at least one matrix representing a two-port, generating gain, noise, and stability functions of a system comprising the two-port, a generator connected to one port of the two-port, the generator having a generator reflectance, and a load... | 04/26/2011 |
| 7930662 | Methods for automatically generating fault mitigation strategies for electronic system designs Approaches for generating a design of an electronic system are disclosed. In one approach, for each of one or more components of a first specification of the design, an error mitigation technique is selected from among multiple different error mitigation techniques ... | 04/19/2011 |
| 7926015 | Optimization method for fractional-N phased-lock-loop (PLL) system In one general embodiment, a method is provided. In operation, a first phase noise in a first circuit located on an integrated circuit is determined. Additionally, a second phase noise in a second circuit coupled to the first circuit but which is not located in the ... | 04/12/2011 |
| 7921398 | System and medium for placement which maintain optimized timing behavior, while improving wireability potential A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list.... | 04/05/2011 |
| 7921402 | FPGA circuits and methods considering process variations Methods are described herein which consider both die-to-die and within-die variations in effective channel length, threshold voltage, and gate oxide thickness, based on first developing closed-form models of chip level FPGA leakage and timing variations. Execution t... | 04/05/2011 |
| 7912694 | Print events in the simulation of a digital system According to a method of simulation processing, one or more HDL source files describing a digital design including a plurality of hierarchically arranged design entities are received. The one or more HDL source files include one or more statements instantiating a pl... | 03/22/2011 |
| 7913211 | Logic cell configuration processing method and program A logic cell configuration processing method for a CMOS semiconductor is configured in which leak current per unit width equal for P-channel and N-channel MOS transistors, by calculating a probable average leak current, which is an expected value of leak current of ... | 03/22/2011 |
| 7913204 | High-level synthesis apparatus, high-level synthesis system and high-level synthesis method A high-level synthesis apparatus for automatically generating a register transfer level (RTL) logic circuit from a behavioral description has a scheduling unit configured to perform data flow analysis and scheduling to generate a data flow graph showing an operation... | 03/22/2011 |
| 7904857 | Computer-aided design system to automate scan synthesis at register-transfer level A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL tes... | 03/08/2011 |
| 7895558 | Configuration specification language supporting arbitrary mapping functions for configuration constructs A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design... | 02/22/2011 |
| 7886255 | Method for design of programmable data processors A method of integrated circuit programmed data processor design includes selecting a benchmark application, selecting an initial set of architecture parameters, reconfiguring a compiler for the selected architecture parameters, compiling the benchmark, reconfiguring... | 02/08/2011 |
| 7752026 | Tracking converge results in a batch simulation farm network A system and computer program product for providing centralized access to count event information from testing of a hardware simulation model within a batch simulation farm which includes simulation clients and an instrumentation server. Count event data for said ha... | 07/06/2010 |
| 7720665 | Method and system for realizing reset in discrete event simulation A system for controlling reset in discrete event simulation is disclosed. The system includes a simulator configured to effect the discrete event simulation, the simulator having a plurality of shared executable files, a memory configured to store the simulator for ... | 05/18/2010 |
| 7647219 | Event-driven test framework A modular instance-aware event-driven test framework is described. It includes an event-driven test framework, a transition-graph test model for the event-driven text framework, an instance-aware event-driven test framework built on said event-driven test framework ... | 01/12/2010 |
| 7571088 | Simulation of connected devices Simulating device interactions. A method may be practiced in a computing system for simulating interconnected devices. The method of simulating device interactions may be done in performing an overall transaction to obtain an output of system performance characteris... | 08/04/2009 |
| 7567893 | Clock simulation system and method A simulation system, a computer product to implement a simulation method, and a method of simulating a digital circuit that has at least one element and at least one clock signal having clock attributes. The method includes maintaining a data structure for time-sche... | 07/28/2009 |
| 7555417 | Selectively reducing the number of cell evaluations in a hardware simulation An electrical circuit comprising a plurality of cells can be simulated to produce simulation results by sorting cells between active status cells and inactive status cells and reducing the processing of simulation results from inactive cells to thereby save simulati... | 06/30/2009 |
| 7552043 | Method, system and program product for selectively removing instrumentation logic from a simulation model According to a method of simulation processing, a simulation model is received that includes a plurality of design entity instances modeling a digital system and one or more instrumentation entity instances, separate from the plurality of design entity instances, th... | 06/23/2009 |
