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| Number | Title | Issue Date |
| 8117568 | Apparatus, method and computer program product for fast simulation of manufacturing effects during integrated circuit design Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating t... | 02/14/2012 |
| 8112264 | Simulating circuits using network tearing A circuit is simulated by using system or network tearing to obtain a real solution. The circuit may be an entire integrated circuit, portion of an integrated circuit, or a circuit block. A circuit simulation technique of the invention generates a system graph, find... | 02/07/2012 |
| 8108194 | Peak power detection in digital designs using emulation systems A method of analyzing power consumption for a DUT (device under test) that includes an integrated circuit or an electronic system includes: providing emulation data for states of the DUT in one or more time windows; determining operational mode values from the emula... | 01/31/2012 |
| 8099693 | Methods, systems, and computer program product for parallelizing tasks in processing an electronic circuit design Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method loads the full design database information on the master; distributes t... | 01/17/2012 |
| 8099269 | Two-step simulation methodology for aging simulations The present invention is a method and system for simulating the aging process of a circuit. A two-step process is employed whereby, in a first simulation step, a simulation is conducted to obtain node voltages for the original circuit and the node voltages are store... | 01/17/2012 |
| 8099270 | Simulation model for transistors Various embodiments include methods and apparatus for simulating a transistor using a simulation model that includes a transistor simulation model coupled to diode simulation model. ... | 01/17/2012 |
| 8095352 | System and method for automatic selection of transmission line macromodels Transmission line macromodels can be classified into main categories of delay-extraction and rational approximation. The exponential solution of the Telegrapher's Equation is used to create a system and method that enable a time-domain circuit simulator to automatic... | 01/10/2012 |
| 8095353 | Power index computing apparatus, method of computing power index, and computer product A power index computing apparatus that computes a power index for a circuit having one or more modules includes an obtaining unit that obtains estimated power consumption for a module in the circuit and a first computing unit that computes entropy based on a transit... | 01/10/2012 |
| 8095351 | Modeling method, apparatus, and computer readable medium for creating three-dimensional analysis model of a target object to analyze data transmission A modeling method creates a three-dimensional analysis model of a target object for extracting parameters that are used to analyze a high-frequency transmission, by selecting, from an art work data of the target object, an extraction target region that becomes a tar... | 01/10/2012 |
| 8091057 | Synthesis, place, and route responsive to reasons for critical paths not meeting performance objective Methods are provided for implementing a design of an integrated circuit meeting a performance objective. A timing analysis for the design specifies critical timing paths that do not meet the performance objective. Reasons are determined for the critical timing paths... | 01/03/2012 |
| 8086435 | Method for predicting simultaneous switching output (SSO) noise A method for the prediction of simultaneous switching output (SSO) noise that may be generated by one or more signal conduction paths within an electrical system. Electrical disturbance waveforms are first recorded for each signal conduction path that may be affecte... | 12/27/2011 |
| 8082139 | Displaying signals of a design block emulated in hardware co-simulation Methods and systems for simulating an electronic system in a high level modeling system (HLMS). A design block and certain signals of the electronic system are selected. The selected signals include internal signals of the design block that are not ports of the desi... | 12/20/2011 |
| 8082138 | Automated bottom-up and top-down partitioned design synthesis An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partitio... | 12/20/2011 |
| 8078447 | Charge-based miller coefficient computation A method of estimating a Miller coefficient for an aggressor network and a victim network coupled by a coupling capacitor includes synthesizing a reduced order system from the aggressor network and the victim network, estimating an active area across the coupling ca... | 12/13/2011 |
| 8078446 | Linear time-invariant system modeling apparatus and method of generating a passive model A linear time-invariant system modeling apparatus comprises a processing resource arranged to receive, when in use, model data constituting to a model of a linear time-invariant system. The model data includes residual value data and scattering data. The processing ... | 12/13/2011 |
| 8073668 | Method and apparatus for testing a full system integrated circuit design by statistical fault injection using hardware-based simulation A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interfa... | 12/06/2011 |
| 8073820 | Method and system for a database to monitor and analyze performance of an electronic design Various methods and apparatuses are described that provide instrumentation and analysis of an electronic design having one or more bus interconnects. A relational database may have defined tables designed for interconnect analysis of transactions occurring between i... | 12/06/2011 |
| 8069025 | Logic simulator and logic simulation method According to one embodiment, a logical circuit to be simulated includes a timing network and a specific logical device. The timing network transmits a logical value change of an input signal in correspondence with an elapse of time or clock number increments. The sp... | 11/29/2011 |
| 8069024 | Replicant simulation In one embodiment, a method comprises partitioning a circuit description into simulateable partitions; sorting the simulateable partitions into classes wherein each simulateable partition included in a given class is equivalent to each other partition in the given c... | 11/29/2011 |
| 8065130 | Method for message processing on a programmable logic device Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of an integrated circuit is configured to have a plurality of thread circuits and a memory. Messages are received to th... | 11/22/2011 |
| 8065129 | Methods and apparatuses for circuit simulation Methods and apparatuses for transient simulation of circuits. One embodiment of the present invention eliminates the inductive branch current variables in terms of node voltage variables to generate a linear equation system with a sparse, symmetric and positive defi... | 11/22/2011 |
| 8065128 | Methods and apparatus for automated testbench generation Methods and apparatus are provided for efficiently generating designs for testing design automation tools and applications. Randomized and diverse test designs with realistic attributes are automatically generated to allow comprehensive testing of design automation ... | 11/22/2011 |
| 8060355 | Automatic, hierarchy-independent partitioning method for transistor-level circuit simulation A method of providing simulation results includes detecting any power net and rail in a circuit netlist. The circuit can be divided into net-partitioned blocks. Using these net-partitioned blocks, a topological analysis can be performed to identify cuttable/un-cutta... | 11/15/2011 |
| 8050902 | Reporting temporal information regarding count events of a simulation At a simulation client, a design is simulated utilizing a hardware description language (HDL) simulation model by stimulating the HDL simulation model with a testcase. The HDL simulation model includes instrumentation not forming a portion of the design that include... | 11/01/2011 |
| 8051393 | Gate modeling for semiconductor fabrication process effects In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined. The object includes a width and a length in t... | 11/01/2011 |
| 8050901 | Prediction and control of NBTI of integrated circuits A modeling system for modeling integrated circuits includes a process variation generator for generating a first statistic distribution of a process parameter; a performance parameter distribution generator for generating a second distribution of a performance param... | 11/01/2011 |
| 8041552 | Behavioral modeling of high speed differential signals based on physical characteristics A method of modeling the output drivers in an integrated circuit, for example a serializer/deserializer circuit, is provided. In accordance with embodiments of the invention, at least one parameter of the circuit is physically measured and a behavioral model utilizi... | 10/18/2011 |
| 8041553 | Generic software simulation interface for integrated circuits A computer-based system for testing a circuit design for implementation within an integrated circuit device can include a design application (205) providing simulation instructions for testing a circuit design and a simulation driver (225) receiving th... | 10/18/2011 |
| 8037446 | Methods for defining evaluation points for optical proximity correction and optical proximity correction methods including same Methods are disclosed for defining evaluation points for use in optical proximity correction of a rectangular target geometry. A method for defining evaluation points for use in optical proximity correction of a rectangular target geometry may comprise predicting a ... | 10/11/2011 |
| 8032349 | Efficient methodology for the accurate generation of customized compact model parameters from electrical test data Disclosed herein are embodiments of an automated, fast and efficient method of generating a customized compact model that represents a semiconductor device at the chip, wafer or multi-wafer level in a specific manufacturing environment. Specifically, measurement dat... | 10/04/2011 |
| 8032350 | Techniques for generating and simulating a simulatable vector having amplitude noise and/or timing jitter added thereto Methods for generating realistic waveform vectors with controllable amplitude noise and timing jitter, simulatable in a computer-based simulation environment are disclosed. In one implementation, a transition vector is created from a sequence of bits having a rise t... | 10/04/2011 |
| 8028256 | System and method for breaking a feedback loop using a voltage controlled voltage source terminated subnetwork model A system and method is disclosed for breaking a feedback loop by replacing at least one component in the feedback loop with a model containing two physically disconnected subnetworks that have terminals that are connected to ground with voltage controlled, voltage s... | 09/27/2011 |
| 8027826 | Evaluation device consisting of a logic simulator and a simulation result table Evaluation by logic simulation can be favorably performed. A target packet determination part determines if a target packet which is a response packet that is to be transmitted with respect to a request packet that is received is in a simulation result table. When t... | 09/27/2011 |
| 8024168 | Detecting X state transitions and storing compressed debug information A method of generating debug data in a simulation environment includes generating a listing of one or more signals that relate to a failure signal; monitoring simulation data of the one or more signals for transitions between a defined state and an undefined state; ... | 09/20/2011 |
| 8024691 | Automata unit, a tool for designing checker circuitry and a method of manufacturing hardware circuitry incorporating checker circuitry The present invention relates to an automata unit, a tool for designing circuitry and/or checker circuitry, and a method for manufacturing hardware circuitry. The automata unit includes an input unit for receiving assertions using Boolean expressions, an automata ge... | 09/20/2011 |
| 8024694 | Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing at least one representative benchmark circuit, (2) establishing standard sensitization and... | 09/20/2011 |
| 8019586 | Hole query for functional coverage analysis Functional coverage techniques during design verification using cross-product coverage models and hole analysis are enhanced by the use of coverage queries. After running a test suite, a core set of non-covered events is specified. A coverage query is then automatic... | 09/13/2011 |
| 8020125 | System, methods and apparatus for generation of simulation stimulus A method and apparatus for producing a verification of digital circuits is provided. In an exemplary embodiment, a set of Boolean and Integer constraints are derived, and a set of Boolean and Integer stimuli are generated that meet the constraints. These stimuli are... | 09/13/2011 |
| 8019585 | Systems and methods for critical node filtering of integrated circuits Systems, apparatuses, methods, and computer program products for performing silicon debugging and isolating faults in integrated circuits are disclosed. Some embodiments comprise a simulator to simulate operation of one or more portions of a circuit in order to iden... | 09/13/2011 |
| 8020135 | Manufacturing aware design and design aware manufacturing of an integrated circuit Some embodiments of the invention provide a process for designing and manufacturing an integrated circuit (“IC”). The process selects a wiring configuration and an illumination configuration. The process uses the selected wiring configuration to design an IC lay... | 09/13/2011 |
