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| Number | Title | Issue Date |
| 8150648 | Timing generator A delay setting data generator generates delay setting data based on rate data. A variable delay circuit delays the test pattern data by a delay time determined by the delay setting data with reference to a predefined unit amount of delay. First rate data designates... | 04/03/2012 |
| 8108174 | Versatile semiconductor manufacturing controller with statistically repeatable response times The present invention relates to process I/O controllers for semiconductor manufacturing to which a tool host can delegate data collection, monitoring and control tasks. In particular, it relates to process I/O controllers that can perform more than one of data coll... | 01/31/2012 |
| 7908110 | Test device, test method and computer readable media Provided is a test apparatus, including a storage section that stores a count value for adjusting a phase of a sampling clock indicating a timing of acquiring an output signal of a DUT; a clock generating section that generates the sampling clock indicating the timi... | 03/15/2011 |
| 7809521 | Precise delay measurement through combinatorial logic A high resolution circuit and method for facilitating precise measurement of on-chip delays for FPGAs for reliability studies. The circuit embeds a pulse generator on an FPGA chip having one or more groups of LUTS (the “LUT delay chain”), also on-chip. The circu... | 10/05/2010 |
| 7769559 | Instrument with interface for synchronization in automatic test equipment A test system with multiple instruments. Some instruments act as controller instruments and others act as controlled instruments. Each instrument includes a clock generator that synthesizes one or more local clocks from a reference clock. The reference clock is a re... | 08/03/2010 |
| 7672805 | Synchronization of modules for analog and mixed signal testing in an open architecture test system A method and apparatus for synchronizing digital and analog/mixed signal modules in a test site of an open architecture test system is disclosed. Event triggers from digital modules are routed to an ASYNC module, which selectively distributes them to analog/mixed si... | 03/02/2010 |
| 7620516 | Versatile semiconductor manufacturing controller with statistically repeatable response times The present invention relates to process I/O controllers for semiconductor manufacturing to which a tool host can delegate data collection, monitoring and control tasks. In particular, it relates to process I/O controllers that can perform more than one of data coll... | 11/17/2009 |
| 7539592 | Test apparatus and electronic device A test apparatus for testing a device under test is provided. The test apparatus includes: a timing data output section for outputting timing data to define at least one of a timing of modifying a test signal provided to the device under test and a timing of acquiri... | 05/26/2009 |
| 7532995 | Interpolator testing circuit An interpolator testing system comprises an interpolator that generates M clock signals having phase shifts in increments of 360/M degrees relative to a reference clock signal and that outputs one of the M clock signals as a recovered clock signal. A recovered clock... | 05/12/2009 |
| 7526399 | Method of delay calculation in integrated circuit, and timing analysis system using the same In a method of delay calculation of relative timing paths of an integrated circuit, each of the paths contains at least one stage. The method is achieved by calculating an on-chip variation depending on a systematic component and an on-chip variation depending on a ... | 04/28/2009 |
| 7505862 | Apparatus and method for testing electronic systems The technology and economics of system testing have evolved to the point where a radical change in methodology is needed for effective functional testing of systems at clock rates of 1 GHz and higher. Rather than providing a test fixture to interface between the sys... | 03/17/2009 |
| 7454306 | Frequency margin testing A technique for performing frequency margin testing of communications system circuit boards incorporates a frequency agile clock source on a communications system circuit board. The clock source may be programmed to operate the circuit board at a nominal operating f... | 11/18/2008 |
| 7444570 | Apparatus and method for controlling frequency of an I/O clock for an integrated circuit during test A test system including a device under test (DUT) and a tester, where the DUT includes I/O interface logic and a clock circuit. The clock circuit includes a core clock circuit, a pad clock circuit, a test clock circuit, and a select circuit. The core clock circuit g... | 10/28/2008 |
| 7415377 | Relay testing system and method A programmable system for testing relays and controlling systems is provided. In one embodiment the present disclosure provides a programmable device capable of, for example, testing relays. The device includes a signal generator for generating signals to test relay... | 08/19/2008 |
| 7382366 | Method, apparatus, system, and graphical user interface for selecting overclocking parameters of a graphics system Overclocking parameters in a graphics system are automatically set. In one embodiment, in response to a user request, overclocking parameters for different sets of overclocking parameters are tested using a graphical stress test to select optimum overclocking parame... | 06/03/2008 |
| 7373561 | Integrated packet bit error rate tester for 10G SERDES An integrated packet bit error rate tester includes a packet transmit circuit that has a first memory for storing transmit packet data and is connectable to a channel under test. A packet receive circuit includes a second memory for storing received packet data and ... | 05/13/2008 |
| 7369957 | Method and system for generating test pulses to test electronic elements A method and system for generating test pulses to test electronic elements are disclosed. After determining a transmission clock, which is smaller than a test clock, and a serial of predetermined pulses, the serial of data bits corresponding to the serial of predete... | 05/06/2008 |
| 7366648 | Electronic circuit analyzing apparatus, electronic circuit analyzing method, and electronic circuit analyzing program The present invention provides an electronic circuit analyzing apparatus for evaluating the reliability value of an analysis result, an electronic circuit analyzing method, and an electronic circuit analyzing program. The electronic circuit analyzing apparatus compr... | 04/29/2008 |
| 7330803 | High resolution time interval measurement apparatus and method A time interval measurement apparatus and method counts the total number of full clock time periods between two measurement signals. Clock fractional time periods are generated between each of the two measurement signals and the next leading edge of a full clock tim... | 02/12/2008 |
| 7331027 | Method for swapping circuits in a metal-only engineering change A method is disclosed for improving design criteria and importantly timing criteria following a metal-only engineering change. The method involves making initial logical changes involving new books (gate-level, filler-cell circuits, called ‘eco books’), running ... | 02/12/2008 |
| 7325171 | Measurement and data acquisition system including a real-time monitoring circuit for implementing control loop applications A measurement and data acquisition system including a real-time monitoring circuit for implementing control loop applications. The system control loop may include the real-time monitoring circuit, a data acquisition device, a processing unit, and a plurality of subs... | 01/29/2008 |
| 7324914 | Timing closure for system on a chip using voltage drop based standard delay formats A timing closure analysis associated with SoCs uses voltage drop based standard delay formats (SDFs). Static timing analysis (STA) is implemented using multiple SDFs, one for each mode (ATPG Test, BIST Test, Functional) as contrasted with doing STA with only one wor... | 01/29/2008 |
| 7319936 | Instrument with interface for synchronization in automatic test equipment A test system with multiple instruments. Some instruments act as controller instruments and others act as controlled instruments. Each instrument includes a clock generator that synthesizes one or more local clocks from a reference clock. The reference clock is a re... | 01/15/2008 |
| 7318003 | System and method of determining the speed of digital application specific integrated circuits According to one embodiment of the present invention, a system for identifying a running speed of an integrated circuit is provided. An asynchronous multi-rail circuit is configured to receive input data and transmit output data. A completion detection circuit is co... | 01/08/2008 |
| 7315791 | Application programming interface for synchronizing multiple instrumentation devices An application programming interface (API) for synchronizing multiple devices in a system. The API includes a plurality of functions invocable in a program to synchronize multiple devices, where each function is executable to perform a respective functionality relat... | 01/01/2008 |
| 7315593 | Hyperfine oversampler method and apparatus A plurality of digital samplers operating on a common signal under test (SUT) sample the SUT at a sample rate beyond that which guarantees monotonic sampling and non-overlapping setup and hold windows for adjacent samplers. Subsequent processing of the sample stream... | 01/01/2008 |
| 7308381 | Timing verification method for semiconductor integrated circuit Initially, non-uniformity of statistical skews between a plurality of clock output terminal pairs is calculated. Next, a partial circuit driven by a clock output terminal pair having each skew distribution is extracted from an integrated circuit. Next, a second stat... | 12/11/2007 |
| 7308371 | Bit error rate testing for high-speed devices A method and system for performing a bit error rate test on a device with substantial duty cycle output distortion are described herein. ... | 12/11/2007 |
| 7299437 | Method and apparatus for detecting timing exception path and computer product A selector selects an FF pair (FFs, FFe) in circuit information, a calculator calculates value-capturing condition data at FFe, a divider divides a path set that matches the value-capturing condition data from a set of paths between the FF pair (FFs, FFe), and a mul... | 11/20/2007 |
| 7289926 | System and method for examining high-frequency clock-masking signal patterns at full speed The present invention provides for a method for examining high-frequency clock-masking signal patterns at a reduced frequency. A first mode of a first shift register is selected. A plurality of bits is loaded on the first shift register at a first frequency. A secon... | 10/30/2007 |
| 7283920 | Apparatus and method for testing semiconductor device A phase difference between a timing of rising or falling of the data read from a semiconductor device to be test and a timing of rising or falling of a reference clock outputted synchronized with the data is measured by operating sampling with strobe pulses configur... | 10/16/2007 |
| 7280939 | System and method of analyzing timing effects of spatial distribution in circuits Systems and methods are provided for analyzing the timing of circuits, including integrated circuits, by taking into account the location of cells or elements in the paths or logic cones of the circuit. In one embodiment, a bounding region may be defined around cell... | 10/09/2007 |
| 7278079 | Test head utilized in a test system to perform automated at-speed testing of multiple gigabit per second high serial pin count devices A portion of a test head utilized to perform simultaneous automated at-speed testing of a plurality of devices that generate serial data signals having gigabit per second baud rates. The portion of the test head includes connection sections that couple an external t... | 10/02/2007 |
| 7272539 | Representation generation method, representation generation device, and representation generation system Unique representation, such as music or image full of originality, is generated in relation to a specific data sequence such as a telephone number. A music generation server 10 is provided with a material table TA in which material data associated with... | 09/18/2007 |
| 7257508 | Timing generator, and timing generating method There is provided a timing generator that outputs a second periodic signal having a desired phase difference to a first periodic signal by superimposing a voltage on a control voltage of a voltage-controlled oscillating unit of a PLL circuit for generating the secon... | 08/14/2007 |
| 7251764 | Serializer/deserializer circuit for jitter sensitivity characterization Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To th... | 07/31/2007 |
| 7248986 | Programmable system for device testing and control A programmable system for testing relays and controlling systems is provided. In one embodiment the present disclosure provides a programmable device capable of, for example, testing relays. The device includes a signal generator for generating signals to test relay... | 07/24/2007 |
| 7246018 | Interpolator testing circuit An interpolator testing system and method comprises an interpolator that includes a phase shift module. The phase shift module receives a reference clock signal and generates M clock signals having phase shifts in increments of 360/M degrees relative to the referenc... | 07/17/2007 |
| 7222035 | Method and apparatus for determining changing signal frequency A method and apparatus for estimating the changing frequency of a signal received by a satellite receiver from, illustratively, positioning system satellites is disclosed that enables a more accurate measurement of the change in frequency of that signal due to movem... | 05/22/2007 |
| 7222042 | System and method of measuring turn-on and turn-off times of an optoelectronic device Systems and methods are disclosed measuring the turn-on and turn-off times of an optoelectronic transceiver's transmitter circuitry. The method includes generating a two bit sequences from separate bit sequence generators using the same controlling pattern. The firs... | 05/22/2007 |
