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| Number | Title | Issue Date |
| 8190391 | Determining die performance by incorporating neighboring die performance metrics A method includes receiving a first set of parameters associated with a plurality of die. A first die performance metric associated with a selected die is determined based on the first set of parameters. At least one neighborhood die performance metric associated wi... | 05/29/2012 |
| 8185337 | System, method, and computer program product for testing and re-testing integrated circuits A system, method, and computer program product are provided for testing and re-testing integrated circuits. In use, a group of integrated circuits is tested. In use, before finishing the test, at least one of the integrated circuits of the group is re-tested. ... | 05/22/2012 |
| 8185336 | Test apparatus, test method, program, and recording medium reducing the influence of variations Provided is a test apparatus that tests a device under test, including a vector expanding section that sequentially generates a plurality of test vectors; a predicting section that calculates a predicted value for each test vector by simulating an operation of the d... | 05/22/2012 |
| 8126674 | Memory-daughter-card-testing method and apparatus A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to b... | 02/28/2012 |
| 8041529 | Changing parameters in a tested system using virtual working pages Methods and systems for managing virtual working pages are disclosed. One method includes storing a first set of parameters in a working page within the tested system, where the first set of parameters is used for calibration of the tested system. The method also in... | 10/18/2011 |
| 8041530 | Method to efficiently synchronize multiple measurements across multiple sensor inputs A system for synchronizing multiple measurements across multiple sensors is provided. The system implements an algorithm in combination with highly flexible hardware architecture that generally comprises of multiple sensor inputs correspondingly from multiple sensor... | 10/18/2011 |
| 8027801 | Multi drive test system for data storage device Embodiments of the invention provide a data storage device test method and data storage device manufacture method which allow a tester to perform an operation test of plural data storage devices connected thereto in a shorter period of time. In one embodiment, an op... | 09/27/2011 |
| 8014969 | Test apparatus, test method and manufacturing method There is provided a test apparatus for testing a plurality of devices under test. The test apparatus includes a signal input section that applies a test signal to the devices under test so as to cause the devices under test to concurrently output response signals, a... | 09/06/2011 |
| 8000921 | Method and apparatus for synchronizing signals in a testing system The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal associated with each device under test (DUT) is maintained at an integer multiple of the tester timing signal.... | 08/16/2011 |
| 7991574 | Techniques for filtering systematic differences from wafer evaluation parameters A method, system and computer program product for filtering systematic differences from wafer evaluation parameters provides an efficient visual display and numerical map technique for observing wafer-level process variation. Measurement data is gathered from electr... | 08/02/2011 |
| 7966145 | Integrated circuit and the corresponding test method, computer device and program An integrated circuit is provided, which includes at least one external input, a power supply and a plurality of elementary components, each having at least one internal input and at least one internal output. The circuit further includes at least one test unit havi... | 06/21/2011 |
| 7930129 | Uniform power density across processor cores at burn-in A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process ... | 04/19/2011 |
| 7885782 | Method in an integrated circuit (IC) manufacturing process for identifying and redirecting ICs mis-processed during their manufacture A method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating ICs on the wafers. At probe, a unique fuse ID is stored in each IC, and an electronic wafer map is electronically stored for each wafer indicating the locati... | 02/08/2011 |
| 7848899 | Systems and methods for testing integrated circuit devices Embodiments described herein relate to systems and methods for testing integrated circuit devices within an environment that is representative of the application environment in which an integrated circuit device will be used. In at least one embodiment, the testing ... | 12/07/2010 |
| 7835881 | System, method, and computer program product for testing and re-testing integrated circuits A system, method, and computer program product are provided for testing and re-testing integrated circuits. In use, a group of integrated circuits is tested. In use, before finishing the test, at least one of the integrated circuits of the group is re-tested. ... | 11/16/2010 |
| 7826996 | Memory-daughter-card-testing apparatus and method A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to b... | 11/02/2010 |
| 7822574 | Substrate measuring method, computer-readable recording medium recording program thereon, and substrate processing system In the present invention, substrates in a plurality of lots are successively processed in a coating and developing treatment system, and line width measurement is performed for some of substrates of the substrate which have been through processing in each lot. The l... | 10/26/2010 |
| 7801697 | Method and device for testing communication circuits A novel method for testing a communications circuit is disclosed. The method includes the following steps: (a) connecting an internal balanced circuit to a well-balanced resistor network; (b) measuring a first plurality of real and imaginary components of the voltag... | 09/21/2010 |
| 7716004 | Method and apparatus for matching test equipment calibration A method includes collecting trace data associated with a plurality of device testers. Tester health metrics are generated for each of the device testers. The tester health metrics are analyzed to identify a selected tester health metric that diverges from the plura... | 05/11/2010 |
| 7711513 | System and method of determining the speed of digital application specific integrated circuits According to one embodiment of the present invention, a system for identifying a running speed of an integrated circuit is provided. An asynchronous multi-rail circuit is configured to receive input data and transmit output data. A completion detection circuit is co... | 05/04/2010 |
| 7707000 | Test instrument and system responsive to execution time data Test instruments constituting an automatic test system are characterized in terms of execution time data. The execution time data is composed of a set of execution times. Each of the execution times is the time required for the test instrument to perform a respectiv... | 04/27/2010 |
| 7693676 | Low power scan test for integrated circuits Low power design is a critical concern and metric for integrated circuits. During scan based manufacturing test, electric power dissipation becomes even more critical as the chip may not have been designed to tolerate excessive switching during scan test. Excessive ... | 04/06/2010 |
| 7653505 | Method and apparatus for testing a controlled impedance buffer A method and apparatus is provided to utilize the configurability of a programmable logic device (PLD), so as to reduce the complexity of special test equipment (STE) fixtures that are required to test the PLD. The output drivers of certain I/O buffers of the PLD th... | 01/26/2010 |
| 7653504 | Method and apparatus for providing shorted pin information for integrated circuit testing Method and apparatus for providing shorted pin information for constructing a device under test (DUT) board for integrated circuit testing is described. In one example, an interface to an application module that implements pin-shorting rules associated generally wit... | 01/26/2010 |
| 7650255 | Automatic selective retest for multi-site testers A method of multi-site testing a batch of semiconductor units using a multi-site automated tester (100). The tester (300) includes a handler (320) coupled to a contactor (330) including a first plurality of contact sites. The method inclu... | 01/19/2010 |
| 7620515 | Integrated circuit with bit error test capability An integrated circuit (10), preferably a field programmable gate array—FPGA or an application specific integrated circuit—ASIC—, comprises a level comparator (30) for comparing a level of a comparator input signal and correspondingly providing a ... | 11/17/2009 |
| 7567883 | Method and apparatus for synchronizing signals in a testing system The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal associated with each device under test (DUT) is maintained at an integer multiple of the tester timing signal.... | 07/28/2009 |
| 7512508 | Determining and analyzing integrated circuit yield and quality Methods, apparatus, and systems for computing and analyzing integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein information is received from processing test responses of integrated circuits designed for fu... | 03/31/2009 |
| 7512509 | M1 testable addressable array for device parameter characterization An integrated circuit device and device parameter characterization method are provided. The integrated circuit device has a padset with plurality of pads. The integrated circuit device also includes one or more arrays of devices under test, each of the one or more a... | 03/31/2009 |
| 7463992 | Method and system to self-test single and multi-core CPU systems A method, apparatus, article of manufacture, and system, the method including, in some embodiments, performing an in-system (or in-the-field) self-test on a first core of a multi-core (or multi-CPU) processor to obtain at a value for at least one operational paramet... | 12/09/2008 |
| 7444275 | Multi-variable polynomial modeling techniques for use in integrated circuit design Techniques are disclosed for modeling a cell of an integrated circuit design. In one aspect of the invention, a full-space polynomial model is fit to cell information comprising measured data points associated with one or more independent variables such as voltage s... | 10/28/2008 |
| 7440864 | Controller system for pool and/or spa A method of programming a microcomputer based controller system for a bathing installation. The microcomputer is configured to receive input command and sensor information from a plurality of input devices including a control panel and a bathing installation sensor,... | 10/21/2008 |
| 7440859 | Method for determining plasma characteristics Methods for determining characteristics of a plasma are provided. In one embodiment, a method for determining characteristics of a plasma includes obtaining metrics of a plasma at two different frequencies, and determining at least one characteristic of the plasma u... | 10/21/2008 |
| 7437261 | Method and apparatus for testing integrated circuits A distributed operating system for a semiconductor test system, such as automated test equipment (ATE), is described. The operating system includes a host operating system for enabling control of one or more site controllers by a system controller. One or more local... | 10/14/2008 |
| 7433792 | Disc drive testing system and method A disc drive testing method is provided for testing a plurality of disc drives. The disc drive testing method includes steps of: selecting a disc drive as a current testing disc drive; sending load/unload commands to the current testing disc drive to drive the curre... | 10/07/2008 |
| 7433793 | Error detection apparatus and method and signal extractor A modulated voltage signal modulated at a predetermined frequency f0 is supplied to an integrated circuit under test to be tested set at an arbitrary stationary point, and an observation signal containing information on power supply current flowing through th... | 10/07/2008 |
| 7421384 | Semiconductor integrated circuit device and microcomputer development supporting device During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits i... | 09/02/2008 |
| 7421364 | Integrated circuit device having a test circuit to measure AC characteristics of internal memory macro An integrated circuit device of the invention, has a memory macro which during normal operation latches an input address in response to a control pulse and generates data output corresponding to the input address, and a test control circuit 22 which during te... | 09/02/2008 |
| 7421632 | Mapping logic for controlling loading of the select ram of an error data crossbar multiplexer Methods and circuits for efficient configuration an error data crossover configuration circuit of an integrated circuit tester allows simultaneous DUT channel configuration for multiple identical DUTs for an error data control circuit. ... | 09/02/2008 |
| 7415378 | Methods for analyzing critical defects in analog integrated circuits The present invention provides a method for analyzing critical defects in analog integrated circuits. The method for analyzing critical defects, among other possible steps, may include fault testing a power field effect transistor (120) portion of an analog i... | 08/19/2008 |
