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| Number | Title | Issue Date |
| 8190111 | Two-point polar modulator and method for generating a polar-modulated signal based on amplitude information and phase information A two-point polar modulator for generating a polar-modulated signal based on an amplitude information and a phase information includes a two-point modulation phase-locked loop which is implemented to enable a frequency setting depending on a first control value via ... | 05/29/2012 |
| 8160525 | Method and system for compensating for using a transmitter to calibrate a receiver for channel equalization Aspects of a method and system for compensating for using a transmitter to calibrate a receiver for channel equalization are provided. Various embodiments of the invention may be applicable wireless devices in TDM systems, Bluetooth, and/or WLAN applications, for ex... | 04/17/2012 |
| 8073414 | Auto-tuning system for an on-chip RF filter A Radio Frequency Receiver on a Single Integrated Circuit (“RFSIC”) is described. The RFSIC may include a mixer, a phase-locked loop (“PLL”) in signal communication with the mixer, and an on-chip auto-tuned RF filter in signal communication with both the mix... | 12/06/2011 |
| 8027654 | Digital broadcasting receiving apparatus When a power source of a digital broadcasting receiving apparatus is turned on, a microprocessor executes reading of a Read Data with specifying a Read Slave Address which is set by applying a prescribed electrical potential to an Address Select (AS) terminal, if th... | 09/27/2011 |
| 8005447 | Method and apparatus for providing a dual-loop phase lock loop A method and apparatus for providing a dual-loop phase lock loop (PLL) for a radio-frequency (RF) receiver is provided. The dual-loop PLL may include coarse tuning circuitry and fine tuning circuitry. The coarse turning circuitry and fine tuning circuitry may be arr... | 08/23/2011 |
| 7890070 | Filter circuit arrangement A filter circuit arrangement for filtering of a radio-frequency signal has a first tunable filter and a phase regulation loop in order to hold the first tunable filter to a transmission phase constant relative to the frequency of the radio-frequency signal. The filt... | 02/15/2011 |
| 7437133 | Radio frequency tuner front end and tuner A front end for a radio frequency tuner, for example for connection to a cable distribution network, including an input connected to a signal path comprising an LNA connected via an AGC stage to a signal splitter. The input path has a bandwidth sufficiently wide to ... | 10/14/2008 |
| 7433657 | Apparatus and method for dynamically clocking a loop filter in a digital communications device A transmitter has a signal generator, an amplifier, a detection circuit, a comparison circuit, a loop filter, and an adjustable clock. The signal generator produces a signal. The signal is produced with a first frequency characteristic and contains frequency-related... | 10/07/2008 |
| 7426377 | Sigma delta (ΣΔ) transmitter circuits and transceiver using the same A ΣΔ transmitter that permits setting of a loop filter LF, a charge pump current and other factors to the same conditions even if it is operated in a plurality of frequency bands, therefore allows the number of components to be reduced and at the same time enables... | 09/16/2008 |
| 7412215 | System and method for transitioning from one PLL feedback source to another A system and method are provided for switching from one phase-locked loop feedback source to another in a radio frequency (RF) transmitter. The RF transmitter includes a phase-locked loop (PLL) that provides a phase-modulated RF input signal and power amplifier circ... | 08/12/2008 |
| 7409029 | Transmission device for automatically set an optimal point for a signal decision making There is provided a flexible transmission device capable of automatically setting an optimal point for a signal decision making with high accuracy, so that highly reliable high-quality signal regeneration control is achieved. A clock timing extraction circuit dynami... | 08/05/2008 |
| 7398071 | Loop filter with gear shift for improved fractional-N PLL settling time An integrated circuit radio frequency (RF) transmitter includes a phase locked loop having a multi-mode loop filter that is operable to provide wide band response with a fast settle time in a startup mode of operation and a relatively more narrow response with a lon... | 07/08/2008 |
| 7395044 | Signal processing apparatus and method of differential transformer A measuring apparatus employing a differential transformer includes a high-frequency oscillator which generates a high-frequency signal having a frequency higher than the excitation frequency of the differential transformer, a frequency divider which divides the hig... | 07/01/2008 |
| 7363015 | Wide-frequency-range television tuner A television tuner includes a tuning circuit having two first varactor diodes for changing a tuning frequency, a mixer for converting a television signal to an intermediate frequency signal, an oscillator having a second varactor diode, and a PLL circuit for outputt... | 04/22/2008 |
| 7353009 | Combined transmitter A combined transmission unit for TMDS signals and LVDS signals. First (LVDS) and second (TMDS) transmission units are both coupled to a first set of input terminals. A switching controller, according to a mode selection signal, enables the first transmission unit to... | 04/01/2008 |
| 7349515 | Method and an apparatus to improve production yield of phase locked loops An apparatus and a method for improving production yield of phase locked loops (PLLs) have been disclosed. One embodiment of the apparatus includes a PLL comprising a charge pump and an offset compensation circuit coupled to the charge pump to provide an offset curr... | 03/25/2008 |
| 7342986 | Digital PLL device A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring ... | 03/11/2008 |
| 7343142 | Tuner A digital terrestrial tuner has an RF input connected to a filter arrangement, whose output signal is supplied to a zero intermediate frequency frequency changer. The filter arrangement comprises a plurality of signal paths of different frequency responses. The sign... | 03/11/2008 |
| 7333468 | Digital phase locked loops for packet stream rate matching and restamping A packet stream multiplexer may include one or more control loops (e.g., digital phase locked loops) for tracking the source clock frequency associated with a packet stream. A first control loop may slowly drive an error between a received timestamp and an estimated... | 02/19/2008 |
| 7333789 | Wide-band modulation PLL, timing error correction system of wide-band modulation PLL, modulation timing error correction method and method for adjusting radio communication apparatus having wide-band modulation PLL A broadband modulation PLL includes a PLL portion containing a voltage controlled oscillator (101), a frequency divider (105), a phase comparator (104) and a loop filter (103). A frequency-dividing ratio of the frequency divider (105 | 02/19/2008 |
| 7324795 | Method of controlling phase locked loop in mobile station, and mobile station A method of controlling a phase locked loop in a mobile station and a mobile station of a cellular telecommunications system are provided. The mobile station comprises an integrated phase locked loop for generating output frequencies; a frequency control unit for pr... | 01/29/2008 |
| 7324787 | Method of ramping up output level of power amplifier of radio communication system, communication semiconductor integrated circuit, and radio communication system In a radio communication system having a phase control loop for phase modulation and an amplitude control loop for amplitude modulation and being capable of time divisional transmission and reception under a predetermined time management, when transmission in a firs... | 01/29/2008 |
| 7317905 | Radio-controlled clock and method for gaining time information Time signals for controlling a radio clock are transmitted by a transmitter and received by a receiver as amplitude modulated time signals, formed of a multitude of time frames. Each time frame has a constant duration. These time signals are first automatically ampl... | 01/08/2008 |
| 7315730 | Architecture for a receiver front end having dual output low noise amplifier driving separate pre-selectors coupled to a transformer for single ended output An architecture for a receiver front end utilizes a dual output low noise amplifier (102) driving separate, fixed preselectors (104, 106) coupled to a transformer (108) to generate a single ended output (113). A pair of blocks coupled in ... | 01/01/2008 |
| 7299006 | Adaptive radio transceiver An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged ... | 11/20/2007 |
| 7283796 | Electronic tuning system An electronic tuning system includes an electronic tuner for adjusting the predetermined control voltage of a voltage controlled oscillator (VCO) to tune the local frequency signal to radio waves on an arbitrary channel in accordance with channel selection informati... | 10/16/2007 |
| 7272201 | System for synchronous sampling and time-of-day clocking using an encoded time signal The system for synchronous sampling uses an encoded time signal, such as an IRIG-B signal. The IRIG-B signal is applied to an edge detector, which produces pulses based on the edges of the encoded time signal. These signals are applied to a phase-locked-loop assembl... | 09/18/2007 |
| 7263336 | Device, system and method to provide different bias voltages and common tuning voltage In some embodiments of the present invention, multiple voltage controlled capacitor branches may be employed in a tuning circuit. Each of the multiple voltage controlled capacitors branches may be set to somewhat apart resonance frequency so that a composite resonan... | 08/28/2007 |
| 7263341 | Audio demodulating circuit and television broadcast receiver An audio demodulating circuit in accordance with the present invention for demodulating audio signals in a plurality of broadcast systems of mutually different frequency deviations such as the NTSC and the PAL, is arranged such that a connection between a trap circu... | 08/28/2007 |
| 7260168 | Network measurement method and apparatus The apparatus measures timing variations, such as the jitter or wander in a timing signal (100) of a telecommunications network. A recovered clock signal is sampled and digitized to produce a series of digital clock samples which are then processed (135 | 08/21/2007 |
| 7250821 | Semiconductor integrated circuit A semiconductor integrated circuit capable of performing internal oscillation with high precision is provided. The semiconductor integrated circuit has a memory circuit, an oscillator circuit for generating an internal clock signal based on control information held ... | 07/31/2007 |
| 7248838 | Wireless communication system within a system on a chip A communication system for transmitting data between cores embedded in an integrated circuit on a silicon chip. Communication system includes transmitter circuitry for wirelessly transmitting data between cores and receiver circuitry for wirelessly receiving the tra... | 07/24/2007 |
| 7242916 | Communication semiconductor integrated circuit device and wireless communication system The invention provides a communication semiconductor integrated circuit device (RF IC) capable of pulling in the frequency of a PLL circuit to a desired set frequency at high speed even in the case where a frequency settable range of the PLL circuit is wide without ... | 07/10/2007 |
| 7227912 | Receiver with mirror frequency suppression Receiver comprising an RF front end circuit for a selection and conversion of an RF input signal into a pair of quadrature IF (intermediate frequency) signals being supplied through in-phase and phase quadrature signal paths to signal inputs of quadrature phase dete... | 06/05/2007 |
| 7228116 | Combined transmitter A combined transmission unit for TMDS signals and LVDS signals. A first (LVDS) transmission unit includes a set of first input terminals to receive first data, and a second (TMDS) transmission unit includes a set of second input terminals to receive second data. A p... | 06/05/2007 |
| 7224951 | PMA RX in coarse loop for high speed sampling A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy tha... | 05/29/2007 |
| 7224952 | Charge pump having sampling point adjustment Adjustment circuitry in a phase-locked loop (PLL) adjusts a sampling point to any desired location within a bit period of each bit of received high-speed serial data. The adjustment circuitry, responsive to program control, selectively adds current portions to a cha... | 05/29/2007 |
| 7224639 | Multi-phase clock signal generator and method having inherently unlimited frequency capability A delay-lock loop includes several delay lines, all but the first of which is composed of at least one variable delay unit that provides a fixed delay and a variable delay. The first delay line is composed of a plurality of fixed delay units, but no variable delay u... | 05/29/2007 |
| 7221916 | Signal enhancement device for phase lock loop oscillator A reference signal enhancement device for phase lock loop oscillator. In the reference signal enhancement device, a band pass filtering unit is coupled to a reference signal to filter high frequency noise, low frequency noise, and harmonic components of the referenc... | 05/22/2007 |
| 7184798 | Power conservation system and method A power management circuit is arranged to apply power to and remove power from its own oscillator to conserve power. A power-on reset circuit provides a power-on-reset signal to a state machine. The state machine contains states that are programmed with information ... | 02/27/2007 |
