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| Number | Title | Issue Date |
| 7309638 | Method of manufacturing a semiconductor component A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth s... | 12/18/2007 |
| 7272067 | Electrically-programmable integrated circuit antifuses Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programmi... | 09/18/2007 |
| 7199402 | Semiconductor devices The present invention provides a semiconductor device embracing (a) a first semiconductor region defined by a first end surface, a second end surface opposing to the first end surface and a side boundary surface connecting the first and second end surfaces; (b) a se... | 04/03/2007 |
| 7064090 | Method of manufacturing a semiconductor integrated circuit device A manufacturing technique for a zener diode which includes forming a first semiconductor region in a region such as a well region at a primary face of a semiconductor substrate and then forming a second semiconductor region of opposite conductivity type thereover. T... | 06/20/2006 |
| 7056761 | Avalanche diode with breakdown voltage controlled by gate length In an avalanche structure, different breakdown voltages are achieved by making use of a polygate and forming a highly doped p-n junction beneath the polygate, and adjusting the gate length and optionally the bias voltage of the gate. ... | 06/06/2006 |
| 6900093 | Method of fabricating a zener diode chip for use as a shunt in Christmas tree lighting A process for fabricating Zener diodes that does not require the use of photomasks. An oxide layer is grown on a silicon substrate which is doped with an N-type dopant. The substrate is subsequently implanted with a P-type dopant, forming a PN junction. The substrat... | 05/31/2005 |
| 6897543 | Electrically-programmable integrated circuit antifuses Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programmi... | 05/24/2005 |
| 6894318 | Diode having a double implanted guard ring The present invention provides a diode 200 that includes a substrate 215 doped with a first type dopant and a double implanted guard ring 245 located within the substrate and doped with a second type dopant opposite the first type dopant and hav... | 05/17/2005 |
| 6803598 | Si-based resonant interband tunneling diodes and method of making interband tunneling diodes Interband tunnel diodes which are compatible with Si-based processes such as, but not limited to, CMOS and SiGe HBT fabrication. Interband tunnel diodes are disclosed (i) with spacer layers surrounding a tunnel barrier; (ii) with a quantum well adjacent to, but not ... | 10/12/2004 |
| 6645802 | Method of forming a zener diode An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resisto... | 11/11/2003 |
| 6645820 | Polycrystalline silicon diode string for ESD protection of different power supply connections An ESD protection circuit protects integrated circuits having multiple power supply voltage sources from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage sources. The ESD protection circuit... | 11/11/2003 |
| 6586317 | Method of forming a zener diode in a npn and pnp bipolar process flow that requires no additional steps to set the breakdown voltage A zener diode is formed in a bipolar or BiCMOS fabrication process by modifying the existing masks that are used in the bipolar or BiCMOS fabrication process, thereby eliminating the need for a separate doping step. In addition, the reverse breakdown volt... | 07/01/2003 |
| 6576506 | Electrostatic discharge protection in double diffused MOS transistors The specification describes a DMOS transistor that is fully integrated with an electrostatic protection diode (ESD). The ESD diode is isolated from the DMOS device by a trench. The trench is metallized to tie the guard ring of the ESD to the substrate the... | 06/10/2003 |
| 6555440 | Process for fabricating a top side pitted diode device A method of fabricating a diode device, such as a PIN diode, includes forming top and bottom regions of opposite conductivity types and includes anisotropically etching into the top surface to form a pit having side walls that converge with approach to th... | 04/29/2003 |
| 6552413 | Diode Implemented is a diode which controls an energy loss produced during a reverse recovery operation and generates an oscillation of an applied voltage with difficulty even if a reverse bias voltage has a great value. An N layer 101 and a P layer 102 are for... | 04/22/2003 |
| 6551892 | Process for the manufacture of integrated devices with gate oxide protection from manufacturing process damage, and protection structure therefor A manufacturing process providing a zener diode formed in an N-type well housing a first N-type conductive region and having a doping level higher than the well, and a second P-type conductive region arranged contiguous to the first conductive region. The... | 04/22/2003 |
| 6417061 | Zener diode and RC network combination semiconductor device for use in integrated circuits and method therefor An improved semiconductor device and method which includes a zener diode and RC network combination that share common semiconductor mask steps during the fabrication process. A common N+ layer serves to provide both the separate N+ cathode regions of the ... | 07/09/2002 |
| 6284603 | Flash memory cell structure with improved channel punch-through characteristics A new method of fabricating a Flash EEPROM memory cell is achieved. Ions are optionally implanted into said semiconductor substrate to form threshold enhancement regions of the same type as the semiconductor substrate. A tunneling oxide is formed. A first... | 09/04/2001 |
| 6274909 | Guard ring structure with deep N well on ESD devices In this invention a deep N-type wall is created surrounding an area that contains an ESD device, or circuit. The ESD device, or circuit, is connected to a chip pad and is first surrounded by a P+ guard ring. The P+ guard ring is then surrounded by the dee... | 08/14/2001 |
| 6214666 | Method of forming a non-volatile memory device A method for manufacturing a non-volatile EEPROM memory cell, and a memory cell structure provided by the method. The method comprises the steps of: forming a gate stack on the surface of a substrate; forming a first and a second active regions in the sub... | 04/10/2001 |
| 6051457 | Method for fabricating electrostatic discharge protection device An integrated circuit with a passive component and an ESD device in accordance with the present invention has: a P substrate; an N+ buried layer implanted in the P substrate; a cathode coupled to the N+ buried layer with an N area formed between the catho... | 04/18/2000 |
| 5856214 | Method of fabricating a low voltage zener-triggered SCR for ESD protection in integrated circuits The method in accordance with the present invention is compatible with conventional CMOS fabrication processes to form a zener diode and a lateral silicon controlled rectifier constituting an on-chip ESD protection circuit in a semiconductor substrate. Th... | 01/05/1999 |
| 5851882 | ZPROM manufacture and design and methods for forming thin structures using spacers as an etching mask A cost-competitive, dense, CMOS compatible ZPROM memory array design and method of manufacture is disclosed. The method of manufacture includes a novel method for forming extremely thin diodes and thin strips of other materials such as conductors by using... | 12/22/1998 |
| 5756387 | Method for forming zener diode with high time stability and low noise Zener diode with high stability in time and low noise for integrated circuits and provided in an epitaxial pocket insulated from the rest of a type N epitaxial layer grown on a substrate of type P semiconductor material. In said pocket are included a type... | 05/26/1998 |
| 5686319 | Method for producing a diode In a method for producing a diode, a first, strongly positively doped silicon wafer is bonded in accordance with the silicon fusion method to a second, weakly negatively doped silicon wafer, and subsequently the weakly negatively doped second silicon wafe... | 11/11/1997 |
| 5643820 | Method for fabricating an MOS capacitor using zener diode region A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resist... | 07/01/1997 |
| 5602046 | Integrated zener diode protection structures and fabrication methods for DMOS power devices In one embodiment, modifications to the polysilicon gate, body, source, and contact masks of a DMOS process add a source-body monocrystalline gate protection diode under the gate pad by implanting an anode region beneath the gate. The anode is connected t... | 02/11/1997 |
| 5547880 | Method for forming a zener diode region and an isolation region A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resist... | 08/20/1996 |
| 5486486 | Process for the manufacture of an integrated voltage limiter and stabilizer in flash EEPROM memory devices A process for the manufacture of an integrated voltage limiter and stabilizer component in a flash EEPROM memory device comprises a step of formation of an N type lightly doped well on a single-crystal silicon substrate; a step of formation of an active a... | 01/23/1996 |
| 5468984 | ESD protection structure using LDMOS diodes with thick copper interconnect An interconnection structure and method for a multiple zener diode ESD protectoin circuit for power semiconductor devices. A plurality of lateral Zener diodes is formed. Each device is formed of a plurality of cathode and anode diffusion regions to be cou... | 11/21/1995 |
| 5322803 | Process for the manufacture of a component to limit the programming voltage and to stabilize the voltage incorporated in an electric device with EEPROM memory cells The manufacturing process comprises a first step of formation of an N type sink on a single-crystal silicon substrate, a second step of formation of an active area on the surface of said sink, a third step of implantation of N- dopant in a surface region ... | 06/21/1994 |
| 5179030 | Method of fabricating a buried zener diode simultaneously with other semiconductor devices A method for fabricating a buried zener diode concurrently with other semiconductor devices on a large scale semiconductor wafer includes utilizing a composite mask to define one or more stable buried zener diodes, one or more additional semiconductor dev... | 01/12/1993 |
| 5166089 | Method of making electrostatic discharge protection for semiconductor input devices A method and structure for protecting an integrated circuit from electrostatic discharges are disclosed. A Schottky diode (22) is connected to an input bond pad (12) and to a MOSFET transistor (17) which is desired to be protected. The normally high break... | 11/24/1992 |
| 5089427 | Semiconductor device and method The manufacturing yield and properties of Zener diodes and other PN junctions are improved by locating the main PN junction remote from the die surface and providing at least two shallower concentric P regions of lighter doping surrounding the main P regi... | 02/18/1992 |
| 4978636 | Method of making a semiconductor diode High voltage (200-400 volts) Zener diodes having much improved resistance to degradation under 150° C. HTRB are obtained by a junction passivation comprising a thermal oxide next to the silicon, covered by a TEOS CVD glass, a CVD nitride and a further TE... | 12/18/1990 |
| 4886762 | Monolithic temperature compensated voltage-reference diode and method for its manufacture An improved monolithic, temperature compensated voltage- reference diode is realized by creating a tub of epitaxial semiconductor material in a substrate of opposite conductivity type and creating a voltage reference junction at a surface of the tub. The ... | 12/12/1989 |
| 4835111 | Method of fabricating self-aligned zener diode A method of fabricating a self-aligned zener diode provides for N+ and P+ regions having the large dopant concentrations necessary for compatibility with shallow junction silicon gate CMOS devices. A contact region is provided on the... | 05/30/1989 |
| 4775643 | Mesa zener diode and method of manufacture thereof A mesa Zener diode is described which is manufactured by ion implanting a region of opposite conductivity into a substrate; etching a moat in a surface of the substrate through the region of opposite conductivity; depositing an oxide layer having an openi... | 10/04/1988 |
| 4771011 | Ion-implanted process for forming IC wafer with buried-Zener diode and IC structure made with such process A new process making it possible to produce stable buried Zener diodes in large-sized wafers where slow ramping of diffusion temperatures is required to avoid crystal damage and other adverse effects. The process includes an initial deep ion implantation ... | 09/13/1988 |
| 4758537 | Lateral subsurface zener diode making process A subsurface zener diode is formed in an N type semiconductor substrate such as the kind employed in the epitaxial layer found in silicon monolithic PN junction isolated integrated circuits. A P+ anode is ion implanted into and diffused from an oxide sour... | 07/19/1988 |
