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| Number | Title | Issue Date |
| 7439109 | Method of forming an integrated circuit structure on a hybrid crystal oriented substrate Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. First-type transistors (e.g., NFETs) are formed on first portions of the substrate having a first type of crystalline orientation, and second-typ... | 10/21/2008 |
| 7332418 | High-density single transistor vertical memory gain cell A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate. A source region of a second conductivity type is formed in the substrate extending adjacent to and away f... | 02/19/2008 |
| 7230343 | High density memory array having increased channel widths A memory array having decreased cell sizes and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a ... | 06/12/2007 |
| 7015057 | Method of manufacturing a drive circuit of active matrix device A data holding control signal for each data line is supplied to a plurality of source followers that are connected together in parallel. The parallel-connected source followers are a combination of at least one first follower that is illuminated with laser light onl... | 03/21/2006 |
| 6969662 | Semiconductor device A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate 13. Each of the data storage cells includes a field effect transistor having a source 18, drain 22 and gat... | 11/29/2005 |
| 6844576 | Master slice type semiconductor integrated circuit and method for designing the same A placing and wiring method for a master slice type semiconductor integrated circuit is provided. The method is conducted by an automatic placing and routing apparatus with respect to a master slice 100 having a plurality of basic cells 110 formed in a... | 01/18/2005 |
| 6660595 | Implantation method for simultaneously implanting in one region and blocking the implant in another region A method of fabricating different transistor structures with the same mask. A masking layer (214) has two openings (204, 202) that expose two transistor areas (304,302). The width of the second opening (202) is adjusted such that the angled implant is sub... | 12/09/2003 |
| 6613610 | Image display unit and method of producing image display unit An image display unit and a method of producing the image display unit, wherein the image display unit includes an array of a plurality of light emitting devices for displaying an image, and wherein the method of producing the image display unit employs, ... | 09/02/2003 |
| 6426233 | Uniform emitter array for display devices, etch mask for the same, and methods for making the same The present invention includes a method for making an emitter for a display device, an emitter array produced by such method, an etch mask used during such method, and a method for making such an etch mask. The method for making the emitter is practiced b... | 07/30/2002 |
| 6271081 | Semiconductor memory device Trench capacitors are arranged in the form of a matrix at a constant pitch in row directions while being sequentially shifted between adjacent rows by a predetermined pitch. An element isolating insulator film is formed so as to surround active regions, e... | 08/07/2001 |
| 5770469 | Method for forming semiconductor structure using modulation doped silicate glasses A method of fabricating a semiconductor structure utilizing doped silicate glass on a substrate of a wafer. The method includes the step forming a modulation doped silicate glass structure over a first layer of the wafer. The modulation doped silicate gla... | 06/23/1998 |
| 5698893 | Static-random-access memory cell with trench transistor and enhanced stability A static-random-access memory (SRAM) cell has been devised which contains an access transistor having a first channel region with a first surface that lies along a first crystal plane; and a trench driver transistor having a second channel region with a s... | 12/16/1997 |
| 5652155 | Method for making semiconductor circuit including non-ESD transistors with reduced degradation due to an impurity implant A method for reducing encroachment of an impurity implant into a channel region in a non-ESD transistor in a semiconductor circuit, the non-ESD transistor receiving both first and second implant dopants, and the circuit including a plurality of ESD transi... | 07/29/1997 |
| 5616506 | Semiconductor device having a crystallized silicon thin film in which the crystallization direction is oriented either vertically or horizontally to the current flow direction A silicon film is crystallized in a predetermined direction by selectively adding a metal element having a catalytic action for crystallizing an amorphous silicon and annealing. In manufacturing TFT using the crystallized silicon film, TFT provided such t... | 04/01/1997 |
| 5614426 | Method of manufacturing semiconductor device having different orientations of crystal channel growth In an active matrix type liquid-crystal display device, in a peripheral circuit portion, there is arranged a TFT having a high mobility and capable of allowing a large amount of on-state current to flow. In a pixel portion, there is arranged a TFT having ... | 03/25/1997 |
| 5576223 | Method of defect determination and defect engineering on product wafer of advanced submicron technologies In a method of determining the possible formation of crystalline defects in a body of a semiconductor material during the process of fabricating integrated circuits in the body, at least one body is subjected to a full fabrication process to form complete... | 11/19/1996 |
| 5543337 | Method for fabricating field effect transistor structure using symmetrical high tilt angle punchthrough implants Four electric field containment regions are formed in a semiconductor substrate by implanting ions into the substrate along four axes that are angularly oriented about a normal to a surface of the substrate in four orthogonal directions respectively. The ... | 08/06/1996 |
| 5459085 | Gate array layout to accommodate multi angle ion implantation A transistor gate array includes an active transistor region (50a-50n) of transistor gates all oriented in a single direction. Surrounding the active transistor region on all four sides are input/output regions (52a-52d) each containing a row of input/out... | 10/17/1995 |
| 5432107 | Semiconductor fabricating method forming channel stopper with diagonally implanted ions A silicon dioxide film and a silicon nitride film are sequentially deposited on an n-type silicon substrate in this order. After the silicon nitride film is selectively removed to form openings, an impurity (boron) for forming a channel stopper is diagona... | 07/11/1995 |
| 5040035 | MOS devices having improved threshold match In certain circuits, it is desirable to match the electrical characteristics, (e.g., thresholds), of two (or more) MOS transistors. For example, in an ECL output buffer, a first transistor is a voltage reference, and a second transistor is an output buffe... | 08/13/1991 |
| 4933298 | Method of making high speed semiconductor device having a silicon-on-insulator structure A CMOS silicon-on-insulation structure is fabricated by first forming an insulating SiO2 layer on a silicon substrate having a (110) plane. Openings are then formed in the SiO2 layer to expose a part of the substrate, and a polycryst... | 06/12/1990 |
| 4921812 | Process of fabricating field effect transistor device A process of fabricating a semiconductor integrated circuit device, wherein a semiconductor wafer having a number of isolated active areas has a gate insulator layer located within each active area and defining regions to form source and drain regions, re... | 05/01/1990 |
| 4606113 | Method of manufacturing metal-semiconductor field effect transistors using orientation dependent etched recesses of different depths Field effect transistors are manufactured using a substrate of compound semiconductor material by defining two gate areas which have their longitudinal dimensions so oriented with respect to the crystal axes of the substrate that the substrate material is... | 08/19/1986 |
| 4268848 | Preferred device orientation on integrated circuits for better matching under mechanical stress A system including in combination matched semiconductor elements in a monolithic integrated circuit together with an inexpensive encapsulation. Good electrical matching of individual components in an integrated circuit is achieved by predetermined placeme... | 05/19/1981 |
| 4131496 | Method of making silicon on sapphire field effect transistors with specifically aligned gates The method comprises forming a blind hole in a sapphire substrate using a sulfur hexafluoride gas etchant and an etch mask comprising a single layer of silicon nitride. The blind holes are filled with epitaxially grown silicon and field effect transistors... | 12/26/1978 |
