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| Number | Title | Issue Date |
| 7435651 | Method to obtain uniform nitrogen profile in gate dielectrics The present invention, in one aspect, provides a method of manufacturing a microelectronics device 100 that includes depositing a first gate dielectric layer 160 over a substrate 115, subjecting the first gate dielectric layer 160 to a fi... | 10/14/2008 |
| 7429514 | Use of selective oxidation to form asymmetrical oxide features during the manufacture of a semiconductor device A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor source and drain regions to different doping levels, then performing a t... | 09/30/2008 |
| 7405118 | Semiconductor device and method of fabricating the same The present invention provides a semiconductor device fabrication method including the steps of: forming first gate insulating films in first to third active regions of a silicon substrate; wet-etching the first gate insulating film of the second active region throu... | 07/29/2008 |
| 7402480 | Method of fabricating a semiconductor device with multiple gate oxide thicknesses The individual performance of various transistors is optimized by tailoring the thickness of the gate oxide layer to a particular operating voltage. Embodiments include forming transistors with different gate oxide thicknesses by initially depositing one or more gat... | 07/22/2008 |
| 7388279 | Tapered dielectric and conductor structures and applications thereof Disclosed are tapered dielectric and conductor structures which provide controlled impedance interconnection while signal conductor lines transition from finer pitches to coarser pitches thereby obviating electrical discontinuities generally associated with changes ... | 06/17/2008 |
| 7378308 | CMOS devices with improved gap-filling A semiconductor structure includes a substrate, and a first MOS device on the first region of the substrate wherein the first MOS device includes a first spacer liner. The semiconductor structure further includes a second MOS device on the second region wherein the ... | 05/27/2008 |
| 7378311 | Method of forming memory cells in an array The invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first ac... | 05/27/2008 |
| 7374635 | Forming method and forming system for insulation film A gate insulation film (104) of a MISFET (100) is constituted of a silicon oxide film (106), silicon nitride film (107), and high-permittivity film (108). The silicon oxide film (106) and silicon nitride film (107) ar... | 05/20/2008 |
| 7368790 | Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the... | 05/06/2008 |
| 7348247 | Semiconductor devices and methods of manufacturing the same Semiconductor devices and methods of manufacturing the same are disclosed. A disclosed semiconductor device comprises a semiconductor substrate; a gate formed on the semiconductor substrate; a gate oxide layer interposed between the semiconductor substrate and the g... | 03/25/2008 |
| 7327008 | Structure and method for mixed-substrate SIMOX technology The present invention provides a semiconductor structure that includes a substrate having a crystal lattice; a first structure formed in a first region of the substrate, the first structure includes at least a heterostructure that generates a lattice stress in said ... | 02/05/2008 |
| 7321141 | Image sensor device and manufacturing method thereof A semiconductor substrate is provided on which a plurality of shallow trench isolations (STI) defining a plurality of active areas are formed. The active areas comprise a photo sensing region, and a plurality of photodiodes are formed in each photo sensing region. T... | 01/22/2008 |
| 7300847 | MOS transistor on an SOI substrate with a body contact and a gate insulating film with variable thickness It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gat... | 11/27/2007 |
| 7291534 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device has the steps of: preparing a semiconductor substrate having a structure in which first and second active regions are isolated by a field oxide; forming a first insulation film and a first film on the semiconductor su... | 11/06/2007 |
| 7282426 | Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof A method for forming a semiconductor device including forming a semiconductor substrate; forming a gate electrode over the semiconductor substrate having a first side and a second side, and forming a gate dielectric under the gate electrode. The gate dielectric has ... | 10/16/2007 |
| 7276414 | NAND memory arrays and methods NAND memory arrays and methods are provided. A plurality of first gate stacks is formed on a first dielectric layer that is formed on a substrate of a NAND memory array. The first dielectric layer and the plurality of first gate stacks formed thereon form a NAND str... | 10/02/2007 |
| 7273788 | Ultra-thin semiconductors bonded on glass substrates A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut process on the semiconductor wafer and the glass substrate to provide a thin semiconductor layer bonded to... | 09/25/2007 |
| 7273787 | Method for manufacturing gate dielectric layer A method for manufacturing a gate dielectric layer is provided. A substrate divided into at least a high voltage circuit region and a low voltage circuit region is provided. A first dielectric layer serving as gate dielectric layer in the high voltage circuit region... | 09/25/2007 |
| 7271065 | Horizontal memory devices with vertical gates Structures and methods for memory devices are provided which operate with lower control gate voltages than conventional floating gate transistors, and which do not increase the costs or complexity of the device fabrication process. The novel memory cell includes a s... | 09/18/2007 |
| 7262428 | Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the... | 08/28/2007 |
| 7262103 | Method for forming a salicide in semiconductor device Disclosed is a method for forming salicide in a semiconductor device. The method comprises the steps of: forming a first and a second gate oxide film and in a non-salicide region and a salicide region, the first gate oxide film being thicker than the second gate oxi... | 08/28/2007 |
| 7259071 | Semiconductor device with dual gate oxides A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and... | 08/21/2007 |
| 7208378 | Semiconductor device having multiple gate oxide layers and method of manufacturing thereof A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage leve... | 04/24/2007 |
| 7198974 | Micro-mechanically strained semiconductor film One aspect of the present subject matter relates to a method for forming strained semiconductor film. In various embodiments, a single crystalline semiconductor film is formed on a substrate surface, and a recess is created beneath the film. A portion of the film is... | 04/03/2007 |
| 7172942 | Method for manufacturing semiconductor elemental device The present invention provides a method for manufacturing a semiconductor elemental device wherein a first gate oxide film and a second gate oxide film thicker than the first gate oxide film are formed on a substrate provided with a device forming region comprised o... | 02/06/2007 |
| 7169670 | Method of forming gate oxide layer in semiconductor device Provided is related to a method of forming a semiconductor device comprises steps of: providing a semiconductor substrate having a low voltage region and a high voltage region; forming a pad oxide layer and a pad nitride layer in sequence on the semiconductor substr... | 01/30/2007 |
| 7166185 | Forming system for insulation film The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna. ... | 01/23/2007 |
| 7153753 | Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the... | 12/26/2006 |
| 7151031 | Methods of fabricating semiconductor devices having gate insulating layers with differing thicknesses Semiconductor devices include a first gate pattern on a first active area of a semiconductor substrate. The first gate pattern has a top width that is substantially the same as or less than a bottom width of the first gate pattern. A second gate pattern is provided ... | 12/19/2006 |
| 7118974 | Method of generating multiple oxides by plasma nitridation on oxide A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is gro... | 10/10/2006 |
| 7115480 | Micromechanical strained semiconductor by wafer bonding One aspect disclosed herein relates to a method for forming a strained semiconductor structure. In various embodiments of the method, a number of recesses are formed in a surface of a first semiconductor wafer such that the surface of the first semiconductor wafer h... | 10/03/2006 |
| 7112486 | Method for fabricating semiconductor device by using radical oxidation The present invention provides a method for fabricating a semiconductor device having a dual gate dielectric structure capable of obtaining a simplified process and improving device reliability. The method includes the steps of: forming an insulation layer on a subs... | 09/26/2006 |
| 7084453 | Method of forming different oxide thickness for high voltage transistor and memory cell tunnel dielectric A semiconductor memory device and method for making the same, where a memory cell and high voltage MOS transistor are formed on the same substrate. An insulating layer is formed having a first portion that insulates the control and floating gates of the memory cell ... | 08/01/2006 |
| 7084035 | Semiconductor device placing high, medium, and low voltage transistors on the same substrate A method for forming three kinds of MOS transistors on a single semiconductor substrate, each provided with gate oxides different in thickness from each other, without detracting from the device characteristics. The method includes the steps of forming a dielectric ... | 08/01/2006 |
| 7071038 | Method of forming a semiconductor device having a dielectric layer with high dielectric constant A method for forming a semiconductor device (10) creates a dielectric layer (18) with high dielectric constant. An interfacial layer (14) is formed over a semiconductor substrate (12). A dielectric layer (16) is formed over the int... | 07/04/2006 |
| 7060588 | Semiconductor device using shallow trench isolation and method of fabricating the same A semiconductor device adopting shallow trench isolation for reducing an internal stress of a semiconductor substrate. The semiconductor device is composed of a semiconductor substrate provided with a trench for isolation, and an insulating film formed to cover the ... | 06/13/2006 |
| 7056783 | Multiple operating voltage vertical replacement-gate (VRG) transistor An architecture for creating multiple operating voltage MOSFETs. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and first and second spaced-apart doped regions formed in the surface. A third doped r... | 06/06/2006 |
| 7056791 | Method of forming an embedded flash memory device A method of fabricating an embedded flash memory device. A substrate having a memory area is provided. A device is formed on the substrate in the memory area. A conductive layer is formed over the substrate to cover the device in the memory area. A conformal insulat... | 06/06/2006 |
| 7041562 | Method for forming multiple gate oxide thickness utilizing ashing and cleaning Embodiments of the present invention relate to semiconductor structures having multiple gate dielectric structures. One embodiment forms semiconductor devices in multiple regions having different dielectric thicknesses where the interface between the gate dielectric... | 05/09/2006 |
| 7015111 | Use of selective oxidation to form asymmetrical oxide features during the manufacture of a semiconductor device A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor source and drain regions to different doping levels, then performing a t... | 03/21/2006 |
