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| Number | Title | Issue Date |
| 7405119 | Structure and method for a sidewall SONOS memory device A system and method for a sidewall SONOS memory device is provided. An electronic device includes a non-volatile memory. A substrate includes source/drain regions. A gate stack is directly over the substrate and between the source/drain regions. The gate stack has a... | 07/29/2008 |
| 7374635 | Forming method and forming system for insulation film A gate insulation film (104) of a MISFET (100) is constituted of a silicon oxide film (106), silicon nitride film (107), and high-permittivity film (108). The silicon oxide film (106) and silicon nitride film (107) ar... | 05/20/2008 |
| 7338850 | Method for manufacturing device isolation film of semiconductor device A method for manufacturing device isolation film of semiconductor device is disclosed. The method utilizes a plasma oxidation of a liner nitride film exposed by etching a liner oxide the film in peripheral region prior to the formation of device isolation film to pr... | 03/04/2008 |
| 7323384 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor memory device comprises the steps of: preparing a semiconductor substrate having a gate insulation film and a gate electrode, the gate insulation film being formed on a predetermined active region in the semiconductor substr... | 01/29/2008 |
| 7303959 | Bottom-gate SONOS-type cell having a silicide gate A bottom-gate thin film transistor having a silicide gate is described. This transistor is advantageously formed as SONOS-type nonvolatile memory cell, and methods are described to efficiently and robustly form a monolithic three dimensional memory array of such cel... | 12/04/2007 |
| 7288452 | Method for manufacturing semiconductor device A method of manufacturing a semiconductor device including forming an ONO film on a semiconductor substrate and a hard mask layer on the ONO film, forming a trench by etching the hard mask layer and the ONO film on a field region of the semiconductor substrate using... | 10/30/2007 |
| 7262103 | Method for forming a salicide in semiconductor device Disclosed is a method for forming salicide in a semiconductor device. The method comprises the steps of: forming a first and a second gate oxide film and in a non-salicide region and a salicide region, the first gate oxide film being thicker than the second gate oxi... | 08/28/2007 |
| 7250337 | Method for fabricating a nonvolatile sonos memory device A nonvolatile memory device and a method for fabricating the same is disclosed, to prevent a “smiling” phenomenon in an ONO layer, thereby improving the programming and erasing characteristics, reliability and yield. The device generally includes a semiconductor... | 07/31/2007 |
| 7223659 | Memory device and fabrication method thereof A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer a... | 05/29/2007 |
| 7223658 | Flash memory structure and method for fabricating the same A flash memory structure comprises a semiconductor substrate having a V-groove, a first doped region positioned in the semiconductor substrate, two second doped regions positioned in the semiconductor substrate and at two sides of the V-groove, a dielectric stack ha... | 05/29/2007 |
| 7205186 | System and method for suppressing oxide formation A system and method for suppressing sub-oxide formation during the manufacturing of semiconductor devices (such as MOSFET transistor) with high-k gate dielectric is disclosed. In one example, the MOSFET transistor includes a gate structure including a high-k gate di... | 04/17/2007 |
| 7202128 | Method of forming a memory device having improved erase speed A method of forming a memory device includes forming a memory stack on a substrate. The memory stack includes an alumina layer acting as an intergate dielectric layer. A transistor is formed on the substrate in an area separate from the memory stack. The transistor ... | 04/10/2007 |
| 7199007 | Non-volatile memory device having a nitride barrier to reduce the fast erase effect A method is provided for forming a non-volatile memory device. The method includes forming a stacked structure including a tunnel oxide layer, a floating gate, a thin oxide layer, and a control gate on a semiconductor substrate. Etching is used to define the sidewal... | 04/03/2007 |
| 7192894 | High performance CMOS transistors using PMD liner stress A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nit... | 03/20/2007 |
| 7183158 | Method of fabricating a non-volatile memory A method of fabricating a nonvolatile memory is provided. The method includes forming a bottom dielectric layer, a charge trapping layer, a top dielectric layer and a conductive layer on the substrate sequentially. Portions of conductive layer, top dielectric layer,... | 02/27/2007 |
| 7183143 | Method for forming nitrided tunnel oxide layer A method for forming a nitrided tunnel oxide layer is described. A silicon oxide layer as a tunnel oxide layer is formed on a semiconductor substrate, and a plasma nitridation process is performed to implant nitrogen atoms into the silicon oxide layer. A thermal dri... | 02/27/2007 |
| 7179709 | Method of fabricating non-volatile memory device having local SONOS gate structure in methods of fabricating a non-volatile memory device having a local silicon-oxide-nitride-oxide-silicon (SONOS) gate structure, a semiconductor substrate having a cell transistor area, a high voltage transistor area, and a low voltage transistor area, is prepared.... | 02/20/2007 |
| 7172940 | Method of fabricating an embedded non-volatile memory device A method of fabricating a non-volatile memory based on SONOS is disclosed. By masking the peripheral circuit area with a reverse ONO photoresist layer, the residual ONO layer that is not covered by a gate within the memory array area is etched away to expose the sub... | 02/06/2007 |
| 7166185 | Forming system for insulation film The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna. ... | 01/23/2007 |
| 7163860 | Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device The present invention, in one embodiment, relates to a process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate having formed thereon a gate stack comprising a charge trapping dielectric charge s... | 01/16/2007 |
| 7154142 | Non-volatile memory device and manufacturing method and operating method thereof A non-volatile memory device having a substrate, an n type well, a p type well, a control gate, a composite dielectric layer, a source region and a drain region is provided. A trench is formed in the substrate. The n type well is formed in the substrate. The p type ... | 12/26/2006 |
| 7144774 | Method of fabricating non-volatile memory A method of fabricating a non-volatile memory includes providing a substrate having a composite dielectric layer, a sacrificial layer and a mask layer sequentially formed thereon. The mask layer is patterned to form a plurality of first openings for exposing a porti... | 12/05/2006 |
| 7118967 | Protection of charge trapping dielectric flash memory devices from UV-induced charging in BEOL processing A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell including a charge trapping dielectric charge storage layer in a semiconductor device; and during pro... | 10/10/2006 |
| 7109084 | Flash memory device and method for fabricating the same A flash memory device and a method for fabricating the same is disclosed that reduces or prevents mis-operation and improves integration, which includes a semiconductor substrate having a field region and an active region; a device isolation layer on the field regio... | 09/19/2006 |
| 7102192 | Semiconductor nonvolatile memory cell array A semiconductor nonvolatile memory cell array includes a plurality of semiconductor nonvolatile memory cells. Each memory cell has a control electrode (30); a pair of impurity diffusion regions (21, 22) to provide first and second main electrodes; a pa... | 09/05/2006 |
| 7098147 | Semiconductor memory device and method for manufacturing semiconductor device After a lower silicon oxide film is formed on a silicon region, a silicon film is formed on the lower silicon oxide film by, for example, a thermal CVD method. Subsequently, the silicon film is completely nitrided by a plasma nitriding method to be replaced by a sil... | 08/29/2006 |
| 7098107 | Protective layer in memory device and method therefor A method for protecting a non-volatile memory device, the method including forming a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and forming a protective layer over at least a portion of the polycide ... | 08/29/2006 |
| 7091088 | UV-blocking etch stop layer for reducing UV-induced charging of charge storage layer in memory devices in BEOL processing A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing over the charge trapping dielectric flash memory cell at least ... | 08/15/2006 |
| 7091551 | Four-bit FinFET NVRAM memory device A four-bit FinFET memory cell, method of fabricating four-bit FinFET memory cell and an NVRAM formed of four-bit FINFET memory cells. The four-bit memory cell including two charge storage regions in opposite ends of a dielectric layer on a first sidewall of a fin of... | 08/15/2006 |
| 7087487 | Method for fabricating nonvolatile memory device and method for fabricating semiconductor device A method, for fabricating a semiconductor device including a memory region and a logic circuit region including a periphery circuit, includes: forming sidewall-like control gates on both side surfaces of a first conductive layer at least in a memory region with an O... | 08/08/2006 |
| 7084454 | Nonvolatile integrated semiconductor memory A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel ... | 08/01/2006 |
| 7074677 | Memory with improved charge-trapping dielectric layer A manufacturing method for a Flash memory includes depositing a first dielectric layer on a semiconductor substrate. A low hydrogen charge-trapping dielectric layer is deposited followed by a second dielectric layer. First and second bitlines are implanted and a wor... | 07/11/2006 |
| 7067434 | Hydrogen free integration of high-k gate dielectrics The present invention pertains to forming a transistor in the absence of hydrogen, or in the presence of a significantly reduced amount of hydrogen. In this manner, a high-k material can be utilized to form a gate dielectric layer in the transistor and facilitate de... | 06/27/2006 |
| 7060594 | Memory device and method of manufacturing including deuterated oxynitride charge trapping structure A method for manufacturing a charge storage stack including a bottom dielectric layer, a charge trapping structure on the bottom dielectric layer, and a top dielectric layer, each comprising silicon oxynitride, are formed using reactant gases that comprise hydrogen,... | 06/13/2006 |
| 7060563 | Local SONOS-type structure having two-piece gate and self-aligned ONO and method for manufacturing the same A local SONOS structure having a two-piece gate and a self-aligned ONO structure includes: a substrate; an ONO structure on the substrate; a first gate layer on and aligned with the ONO structure; a gate insulator on the substrate aside the ONO structure; and a seco... | 06/13/2006 |
| 7053446 | Memory wordline spacer A memory includes a semiconductor substrate and a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited and formed. A doped wordline spacer layer is deposited and a doped wordline spacer is formed adjacent to the... | 05/30/2006 |
| 7049195 | Methods of fabricating non-volatile memory devices The present disclosure is directed to a non-volatile memory device having a SONOS structure and a method of fabricating the same, wherein the non-volatile memory device having the SONOS structure is fabricated using a simple and lower cost method by greatly reducing... | 05/23/2006 |
| 7033957 | ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices Process for reducing charge leakage in a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on the semiconductor substrate to form an oxide/silicon interface having a first oxygen content adjacent the oxide/silic... | 04/25/2006 |
| 7033890 | ONO formation method An ONO formation method comprises the following procedures. First, a bottom oxide layer is formed on a silicon substrate, and then a silicon-rich nitride layer is deposited on the bottom oxide layer. Then, an oxidation process is performed to react with silicon atom... | 04/25/2006 |
| 7029976 | Method for SONOS EFLASH integrated circuit A method of manufacturing a charge storage layer for a SONOS memory device. A feature of the embodiment is the first gate layer is formed over the charge storing layer (ONO) before the charge storing layer is patterned. The first gate layer protects the charge stori... | 04/18/2006 |
