Bizarre Patents
User-operated amusement apparatus for kicking the user's buttocks
An apparatus including a user-operated and controlled apparatus for self-infliction of repetitive blows to the user's buttocks by a plurality of elongated arms bearing flexible extensions that rotate under the user's control.
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| Number | Title | Issue Date |
| 7435536 | Method to align mask patterns Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pit... | 10/14/2008 |
| 7419894 | Gate electrode and manufacturing method thereof, and semiconductor device and manufacturing method thereof The present invention provides a method of manufacturing a gate electrode in which a fine gate electrode can effectively be manufactured by thickening a resist opening for gate electrodes formed by ordinary electron beam lithography so as to reduce opening dimension... | 09/02/2008 |
| 7407824 | Guard ring for improved matching A semiconductor manufacturing method comprises forming a leveling guard ring defining an interior area into which are fabricated one or more devices. In certain embodiments two or more matched devices, such as in a common centroid layout, are fabricated in the inter... | 08/05/2008 |
| 7384874 | Method of forming hardmask pattern of semiconductor device A method of forming a hardmask pattern over a semiconductor device semiconductor device includes forming a first hardmask layer over a semiconductor substrate. First and second structures are formed over the first hardmask layer, the first and second structures form... | 06/10/2008 |
| 7358140 | Pattern density control using edge printing processes A structure fabrication method. The method comprises providing a design structure that includes (i) a design substrate and (ii) M design normal regions on the design substrate, wherein M is a positive integer greater than 1. Next, N design sacrificial regions are ad... | 04/15/2008 |
| 7335542 | Semiconductor device with mushroom electrode and manufacture method thereof A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed ... | 02/26/2008 |
| 7288476 | Controlled dry etch of a film The controlled etch into a substrate or thick homogeneous film is accomplished by introducing a sacrificial film to gauge the depth to which the substrate/thick film has been etched. Optical endpointing the etch of the sacrificial film on the etch stop layer allows ... | 10/30/2007 |
| 7282440 | Integrated circuit contact A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of ... | 10/16/2007 |
| 7253012 | Guard ring for improved matching A semiconductor manufacturing method comprises forming a leveling guard ring defining an interior area into which are fabricated one or more devices. In certain aspects, two or more matched devices, such as in a common centroid layout, are fabricated in the interior... | 08/07/2007 |
| 7238624 | System and method for manufacturing semiconductor devices using a vacuum chamber The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to semiconductor manufacturing using a vacuum chamber. In one example, a method for semiconductor manufacturing includes: providing a photoresist layer for ... | 07/03/2007 |
| 7223703 | Method of forming patterns In forming a mask pattern on a circuit board, a mask pattern of N-layer structure is formed in a region where the mechanical strength of the circuit board needs to be increased. N photosensitive layers are first stacked on a substrate so that they becomes lower in s... | 05/29/2007 |
| 7223645 | Semiconductor device with mushroom electrode and manufacture method thereof A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed ... | 05/29/2007 |
| 7183150 | Resist protect oxide structure of sub-micron salicide process In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet... | 02/27/2007 |
| 7176074 | Manufacturing method of thin film transistor array substrate A manufacturing method of thin film transistor array substrate is provided. A substrate, whereon first, second, and third poly-silicon islands, a gate insulating layer, a plurality of first, second, and third gates, and a first passivation layer have been formed, is... | 02/13/2007 |
| 7172960 | Multi-layer film stack for extinction of substrate reflections during patterning A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus compris... | 02/06/2007 |
| 7074631 | Light emitting device methods A method includes disposing a planarization layer on a surface of a layer of semiconductor material and disposing a lithography layer on a surface of the planarization layer. The method also includes performing nanolithography to remove at least a portion of the pla... | 07/11/2006 |
| 7071121 | Patterned ceramic films and method for producing the same A ceramic film is useful as ion-conducting ceramics, electrodes, hard ceramic coatings, transparent conducting oxides, transparent semiconducting oxides, ferroelectric oxides, and dielectric oxides. The ceramic film may be produced from a liquid precursor solution. | 07/04/2006 |
| 7033960 | Multi-chamber deposition of silicon oxynitride film for patterning Pinholes in a silicon oxynitride film are reduced by PECVD deposition of a plurality of silicon oxynitride sub-layers in a PECVD apparatus containing multiple chambers. Embodiments include forming a layer of amorphous carbon over a conductive layer, such as doped po... | 04/25/2006 |
| 7015136 | Method for preventing formation of photoresist scum A method for preventing formation of photoresist scum. First, a substrate on which a dielectric layer is formed is provided. Next, a non-nitrogen anti-reflective layer is formed on the dielectric layer. Finally, a photoresist pattern layer is formed on the non-nitro... | 03/21/2006 |
| 7008856 | Method for fabricating AND-type flash memory cell A flash memory cell and fabrication method thereof are disclosed. An example fabrication method deposits a pad oxide layer and a pad nitride layer on a semiconductor substrate, patterns the pad nitride layer, implants ions into the substrate to form an ion implant r... | 03/07/2006 |
| 6958292 | Method of manufacturing integrated circuit In order to shorten the period for the development and manufacture of a semiconductor integrated circuit device, at the time of transferring integrated circuit patterns onto a wafer by an exposure process, a photomask PM1 is used which is provided partially w... | 10/25/2005 |
| 6929959 | Manufacturing method of CPP type magnetic sensor having current-squeezing path On a multilayer film formed on a lower electrode layer, a resist layer having cutaway parts at a lower portion is formed, and on parts of the upper surface of the multilayer film which are not overlapped with the resist layer except for areas inside the cutaway part... | 08/16/2005 |
| 6869899 | Lateral-only photoresist trimming for sub-80 nm gate stack The invention relates generally to lithographic patterning of very small features. In particular, the invention relates generally to patterning of semiconductor circuit features smaller than lithographically defined using either conventional optical lithography or n... | 03/22/2005 |
| 6855646 | Plasma polymerized electron beam resist A process for producing a pattern of negative electron beam resist comprises: depositing a layer of plasma polymerized fluoropolymer on a face of a substrate, the plasma polymerized fluoropolymer forming the negative electron beam resist; producing an electron beam;... | 02/15/2005 |
| 6841465 | Method of forming dual damascene pattern in semiconductor device Disclosed is a method of forming the dual damascene pattern in the semiconductor device. After forming the trench, a photoresist pattern in which a via hole region is defined is formed by exposure and development processes in a state that a photoresist is thinly coa... | 01/11/2005 |
| 6815347 | Method of forming a reflective electrode The present invention provides a method of forming a TFT and a reflective electrode having recesses or projections with reduced manufacturing cost and a reduced number of manufacturing steps, and provides a liquid crystal display device to which the method is applie... | 11/09/2004 |
| 6815274 | Resist protect oxide structure of sub-micron salicide process In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet... | 11/09/2004 |
| 6808984 | Method for forming a contact opening A method for forming a contact opening is provided. After forming transistors on a substrate, a stacked resist layer including a resist layer without a silicon element and a resist layer with a silicon element covers the transistors and the substrate. The stacked re... | 10/26/2004 |
| 6790743 | [Method to relax alignment accuracy requirement in fabrication for integrated circuit] A method to relax the alignment accuracy requirement in an integrate circuit manufacturing is described. The method comprises forming a mask layer over a substrate, and the mask layer comprises a plurality of first openings. Thereafter, a buffer layer fills the firs... | 09/14/2004 |
| 6774032 | Method of making a semiconductor device by forming a masking layer with a tapered etch profile A method for making a semiconductor device is described. That method includes forming a sacrificial layer on a substrate, then forming a layer of photoresist on the sacrificial layer. After the photoresist layer is patterned, to form a patterned photoresist layer th... | 08/10/2004 |
| 6759328 | Masks and method for contact hole exposure A mask and method for contact hole exposure. First, a mask including a transparent substrate, a phase shift layer installed on the transparent substrate to define a series of patterns having contact hole areas set in array, an a plurality of metal lines installed on... | 07/06/2004 |
| 6727179 | Method for creating an integrated circuit stage wherein fine and large patterns coexist Successive use is made of a layer of radiation-sensitive resin at points intended to form wide semi-conductor patterns in a still intact layer, under at least one hard mask, then of a resin sensitive to particle bombardment over fine patterns to be formed in this sa... | 04/27/2004 |
| 6713348 | Method for forming an etch mask during the manufacture of a semiconductor device A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxide layer is... | 03/30/2004 |
| 6692977 | Method for manufacturing magnetic head A method is provided for manufacturing a magnetic head for recording information on a magnetic recording medium in the form of a direction of magnetization, which enables manufacture of a magnetic head with gaps between turns of a conductive material cons... | 02/17/2004 |
| 6689665 | Method of forming an STI feature while avoiding or reducing divot formation A method for forming shallow trench isolation (STI) features to reduce or avoid divot formation at STI trench corners including providing a shallow trench isolation (STI) feature included in a semiconductor process surface the STI feature including an ani... | 02/10/2004 |
| 6670280 | Methods of microstructuring ferroelectric materials A method of micro-structuring a surface of a sample of ferroelectric material, the method comprising: (a) taking a sample of ferroelectric material having a -z face which is to be etched; (b) illuminating the -z face with ultraviolet light to define illum... | 12/30/2003 |
| 6664173 | Hardmask gate patterning technique for all transistors using spacer gate approach for critical dimension control An electrical element may be made by providing a hardmask unit that has a double gate stack with a first gate layer, a first hardmask layer formed over the first gate layer, a second gate layer formed over the first hardmask layer, and a second hardmask l... | 12/16/2003 |
| 6653244 | Monolithic three-dimensional structures Three-dimensional structures of arbitrary shape are fabricated on the surface of a substrate through a series of processing steps wherein a monolithic structure is fabricated in successive layers. A first layer of photoresist material is spun onto a subst... | 11/25/2003 |
| 6645868 | Method of forming shallow trench isolation using antireflection layer Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a layer of highly absorbing silicon rich nitride to serve as a hardmask between a semiconductor substrate and a photoresist. The hig... | 11/11/2003 |
| 6624085 | Semiconductor structure, capacitor, mask and methods of manufacture thereof A method of fabricating a mask forms a rectangular opening within etch resistant material that overlays a substrate. The mask preferably comprises two layers of photoresist separated by a layer of light blocking material. One of the layers of photoresist ... | 09/23/2003 |
