Celebrity Inventors
Mark Twain (Samuel L. Clemens) received Patent No. 121,992 for "An Improvement in Adjustable and Detachable Straps for Garments." He later received two more patents: one for a self-pasting scrapbook and one for a game to help players remember important historical dates.
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| Number | Title | Issue Date |
| 7682992 | Resistance variable memory with temperature tolerant materials A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb2Se3, and a metal-chalcogenide layer and methods of forming such a memory device. ... | 03/23/2010 |
| 7422985 | Method for reducing dielectric overetch using a dielectric etch stop at a planar surface A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. In a preferred embodiment, the conductive or semiconductor features are pillars forming vertically oriented diodes. A second dielectric material, diffe... | 09/09/2008 |
| 7397060 | Pipe shaped phase change memory A memory cell device includes a bottom electrode, pipe shaped member comprising phase change material and a top electrode in contact with the pipe-shaped member. An electrically and thermally insulating material is inside the pipe-shaped member. An integrated circui... | 07/08/2008 |
| 7393798 | Resistance variable memory with temperature tolerant materials A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb2Se3, and a metal-chalcogenide layer and methods of forming such a memory device. ... | 07/01/2008 |
| 7394087 | Phase-changeable memory devices and methods of forming the same A phase-changeable memory device includes a substrate having a contact region on an upper surface thereof. An insulating interlayer on the substrate has an opening therein, and a lower electrode is formed in the opening. The lower electrode has a nitrided surface po... | 07/01/2008 |
| 7381982 | Method for fabricating chalcogenide-applied memory A chalcogenide memory cell includes a lower electrode, a chalcogenide layer, and an upper electrode. The lower electrode includes a tapered cavity. The chalcogenide layer is formed in the tapered cavity of the lower electrode. One side of the chalcogenide layer is a... | 06/03/2008 |
| 7378678 | Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a m... | 05/27/2008 |
| 7368384 | Film formation apparatus and method of using the same A method of using a film formation apparatus for a semiconductor process includes a step of removing a by-product film deposited on an inner surface of a reaction chamber of the film formation apparatus. This step is performed while supplying a cleaning gas containi... | 05/06/2008 |
| 7365355 | Programmable matrix array with phase-change material A phase-change material is proposed for coupling interconnect lines an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer between the phase change material and at least one of the lines. The matrix ... | 04/29/2008 |
| 7354793 | Method of forming a PCRAM device incorporating a resistance-variable chalocogenide element A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and devices formed using such a method. ... | 04/08/2008 |
| 7348209 | Resistance variable memory device and method of fabrication Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a resistance variable memory device is provided having at least one tin-chalcogenide layer proximate at least on... | 03/25/2008 |
| 7339185 | Phase change memory device and method for forming the same A phase change memory device includes a mold layer disposed on a substrate, a heating electrode, a filling insulation pattern and a phase change material pattern. The heating electrode is disposed in an opening exposing the substrate through the mold layer. The heat... | 03/04/2008 |
| 7316746 | Crystals for a semiconductor radiation detector and method for making the crystals A method for a growing solid-state, spectrometer grade II-VI crystal using a high-pressure hydrothermal process including the following steps: positioning seed crystals in a growth zone of a reactor chamber; positioning crystal nutrient material in the nutrient zone... | 01/08/2008 |
| 7307267 | Electric device with phase change material and parallel heater The electric device (1, 100) has a body (2, 102) having a resistor (7, 107) comprising a phase change material being changeable between a first phase and a second phase. The resistor (7, 107) has a first electrical resistance when the pha... | 12/11/2007 |
| 7256415 | Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a m... | 08/14/2007 |
| 7235497 | Selective oxidation methods and transistor fabrication methods The invention includes selective oxidation methods and transistor fabrication methods. In one implementation, a selective oxidation method includes positioning a substrate within a chamber. The substrate has first and second different oxidizable materials. The subst... | 06/26/2007 |
| 7214632 | Using selective deposition to form phase-change memory cells A phase-change memory cell may be formed by selectively depositing the lower electrode in the phase-change memory pore. Thereafter, an adhesion-promoting material may be selectively deposited on the selectively deposited lower electrode and the upper surface surroun... | 05/08/2007 |
| 7183567 | Using selective deposition to form phase-change memory cells A phase-change memory cell may be formed by selectively depositing the lower electrode in the phase-change memory pore. Thereafter, an adhesion-promoting material may be selectively deposited on the selectively deposited lower electrode and the upper surface surroun... | 02/27/2007 |
| 7064344 | Barrier material encapsulation of programmable material A method comprising forming as stacked materials on a substrate, a volume of programmable material and a signal line, conformably forming a first dielectric material on the stacked materials, forming a second dielectric material on the first material, etching an ope... | 06/20/2006 |
| 7049154 | Vapor phase growth method by controlling the heat output in the gas introduction region A vapor phase growth method for growing a semiconductor single crystal thin film on a front surface of a semiconductor single crystal substrate (1) while introducing gas into a reaction chamber (11), has a step of performing heating output power contro... | 05/23/2006 |
| 7041611 | Enhancement of fabrication yields of nanomechanical devices by thin film deposition A protective film is applied onto a nanostructural feature supported on a sacrificial layer by energy beam assisted deposit of material from a vapor through which the beam passes. A wet etchant is applied to etch away the sacrificial layer beneath the nanostructural... | 05/09/2006 |
| 7030431 | Metal gate with composite film stack A novel metal gate structure includes a gate oxide layer formed on a surface of a silicon substrate, a doped silicon layer stacked on the gate oxide layer, a CVD ultra-thin titanium nitride film deposited on the doped silicon layer, a tungsten nitride layer stacked ... | 04/18/2006 |
| 7022603 | Method for fabricating semiconductor device having stacked-gate structure A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon... | 04/04/2006 |
| 6936837 | Film bulk acoustic resonator A thin film bulk acoustic resonator comprises a substrate (12) of a silicon single crystal, a base film (13) formed on the substrate (12) and composed of a dielectric film mainly containing silicon oxide, and a piezoelectric stacked structure ( | 08/30/2005 |
| 6830952 | Spacer chalcogenide memory method and device The present invention includes devices and methods to form memory cell devices including a spacer comprising a programmable resistive material alloy. Particular aspects of the present invention are described in the claims, specification and drawings. ... | 12/14/2004 |
| 6815270 | Thin film transistor formed by an etching process with high anisotropy The present invention discloses a thin film transistor and a process for forming thereof by a high anisotropy etching process. A thin film transistor according to the present invention comprises a transistor element including a gate electrode, a gate insulating laye... | 11/09/2004 |
| 6787390 | Electrical and thermal contact for use in semiconductor devices An electrical and thermal contact which includes an intermediate conductive layer, an insulator component, and a contact layer. The insulator component is fabricated from a thermally insulative material and may be sandwiched between the intermediate conductive layer... | 09/07/2004 |
| 6692978 | Methods for marking a bare semiconductor die The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particu... | 02/17/2004 |
| 6690026 | Method of fabricating a three-dimensional array of active media An apparatus comprising control circuitry formed on a substrate, and a plurality of active media coupled to the control circuitry and formed in a plurality of planes over the substrate. A method comprising forming a pair of junction regions on a substrate... | 02/10/2004 |
| 6673647 | Method for growing a solid type II-VI semiconductor material A growth method for a bulk II-VI type semiconductor material, including at least a first component and a second component. The method supplies in a crucible a charge including the components, with proportions of the components being such that the first co... | 01/06/2004 |
| 6653211 | Semiconductor substrate, SOI substrate and manufacturing method therefor A substrate for a semiconductor device includes a crystalline silicon substrate; an insulative silicon compound layer thereon and a crystalline insulation layer on the insulative silicon compound layer, wherein the insulative silicon compound layer contai... | 11/25/2003 |
| 6605821 | Phase change material electronic memory structure and method for forming The invention includes an electronic memory structure. The electronic memory structure includes a substrate. A substantially planar first conductor is formed adjacent to the substrate. An interconnection layer is formed adjacent to the first conductor. A ... | 08/12/2003 |
| 6590236 | Semiconductor structure for use with high-frequency signals High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apar... | 07/08/2003 |
| 6569705 | Metal structure for a phase-change memory device The invention relates to a damascene chalcogenide memory cell structure. The damascene chalcogenide memory cell structure is fabricated under conditions that simplify previous process flows. The damascene chalcogenide memory cell structure also prevents v... | 05/27/2003 |
| 6548397 | Electrical and thermal contact for use in semiconductor devices The electrical and thermal contact fabricated by forming a first layer on a surface of a semiconductor device, depositing a dielectric layer adjacent the first layer, patterning the dielectric layer to define an insulator component, and forming a second l... | 04/15/2003 |
| 6545287 | Using selective deposition to form phase-change memory cells A phase-change memory cell may be formed by selectively depositing the lower electrode in the phase-change memory pore. Thereafter, an adhesion-promoting material may be selectively deposited on the selectively deposited lower electrode and the upper surf... | 04/08/2003 |
| 6495395 | Electrical and thermal contact for use in semiconductor devices An electrical and thermal contact which includes an intermediate conductive layer, an insulator component, and a contact layer. The insulator component is fabricated from a thermally insulative material and may be sandwiched between the intermediate condu... | 12/17/2002 |
| 6294404 | Semiconductor integrated circuit having function of reducing a power consumption and semiconductor integrated circuit system comprising this semiconductor integrated circuit A semiconductor integrated circuit according to the present invention comprises a synchronous SRAM, a signal generation circuit generating a chip selection signal, a clock signal etc. supplied to the synchronous SRAM, a voltage set circuit setting the vol... | 09/25/2001 |
| 5985689 | Method of fabricating photoelectric conversion device having at least one step-back layer A photoelectric conversion device includes a plurality of photoelectric conversion units and a signal output unit. The signal output unit has at least one storage device for storing electrical signals generated by the photoelectric conversion device. A sc... | 11/16/1999 |
| 5920788 | Chalcogenide memory cell with a plurality of chalcogenide electrodes A chalcogenide memory cell with chalcogenide electrodes positioned on both sides of the active chalcogenide region of the memory cell. The chalcogenide memory cell includes upper and lower chalcogenide electrodes with a dielectric layer positioned therebe... | 07/06/1999 |
