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| Number | Title | Issue Date |
| 7682991 | Method of manufacturing silicon carbide semiconductor device A method of manufacturing a silicon carbide semiconductor device includes forming a trench for a MOS gate in an SiC substrate by dry etching. Thereafter, the substrate with the trench is heat treated. The heat treatment includes heating the substrate in an Ar gas at... | 03/23/2010 |
| 7670966 | Method of processing a semiconductor substrate by thermal activation of light elements Method of processing a substrate containing at least one semiconductor of the SiXAY type and comprising at least four separate types of light elements, comprising at least the following steps: carrying out a f... | 03/02/2010 |
| 7510986 | Production method for semiconductor device In a production process for a semiconductor device employing an SiC semiconductor substrate (1), the SiC semiconductor substrate (1) is mounted on a susceptor (23), and a C heating member (3) of carbon is placed on a surface of the SiC se... | 03/31/2009 |
| 7504345 | Method for eliminating defects from semiconductor materials Using a helium cryostat, the temperature for a substrate wafer(s) is reduced to 2.2 Kelvin over a period of twenty-four hours. Next, a soak segment will hold the temperature of the substrate wafer at 2.2 Kelvin for a period of ninety-six hours. At these low temperat... | 03/17/2009 |
| 7326656 | Method of forming a metal oxide dielectric A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first... | 02/05/2008 |
| 7256147 | Porous body and manufacturing method therefor It is an object of the present invention to provide a porous body containing an oxide semiconductor in which more efficient photocatalytic reactions and photoelectrode reactions occur. The present invention relates to a porous body having a network structure skeleto... | 08/14/2007 |
| 7248665 | Prescaler Disclosed is a Dual-Modulus Prescaler (DMP) dividing an input signal into an output signal, comprising: a synchronous counter, including a D-Flip-Flop (DFF), a first NOR-Flip-Flop and a second NOR-Flip-Flop, receiving the input signal, the division ratio thereof bei... | 07/24/2007 |
| 7248484 | Electro-magnetic suppressive structure Embodiments of the present invention provide an electro-magnetic suppressive structure. The electro-magnetic suppressive structure comprises a cover portion and an integrally formed conductive portion. ... | 07/24/2007 |
| 7241647 | Graded semiconductor layer A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion an... | 07/10/2007 |
| 7235427 | Method for treating substrates for microelectronics and substrates obtained by said method An embodiment of a multilayer wafer according to the invention includes a base substrate, a first layer associated with the base substrate, and a second layer on the first layer on side opposite from the base substrate in an axial direction and having a lateral edge... | 06/26/2007 |
| 7227172 | Group-III-element nitride crystal semiconductor device In a Group-III-element nitride semiconductor device including a Group-III-element nitride crystal layer stacked on a Group-III-element nitride crystal substrate, the substrate is produced by allowing nitrogen of nitrogen-containing gas and a Group III element to rea... | 06/05/2007 |
| 7205033 | Method for forming polycrystalline silicon film of polycrystalline silicon TFT Disclosed is a method for forming a polycrystalline silicon film of a polycrystalline silicon thin film transistor. The method includes a step of crystallizing an amorphous silicon film deposited on a glass substrate by irradiating a laser beam onto the amorphous si... | 04/17/2007 |
| 7179678 | EBIC response enhancement in type III-VI semiconductor material on silicon A method of processing a type III–VI semiconductor material on a silicon substrate to improve minority carrier diffusion length and EBIC response is provided. The semiconductor material is heated to a temperature in the range of 300° C.–600° C. for a period in... | 02/20/2007 |
| 7169708 | Semiconductor device fabrication method A method of performing microfabrication using a hard mask in the manufacture of a semiconductor device having an interlayer dielectric (ILD) film made of low-dielectric constant, K, insulating material is provided. When treating a low-K dielectric film for use in se... | 01/30/2007 |
| 7151060 | Device and method for thermally treating semiconductor wafers A device for thermally treating semiconductor wafers having at least one silicon layer to be oxidized and a metal layer, preferably a tungsten layer, which is not to be oxidized. The inventive device comprises the following: at least one radiation source; a treatmen... | 12/19/2006 |
| 7135408 | Metal barrier integrity via use of a novel two step PVD-ALD deposition procedure A method of forming a barrier layer on the surface of an opening defined in a porous, low dielectric constant (low k), layer, has been developed. The method features the use of a two step deposition procedure using a physical vapor deposition (PVD), procedure to ini... | 11/14/2006 |
| 7122476 | Method for fabricating semiconductor device by forming trenches in different depths at a cellregion and a peripheral region for reducing self aligned source resistance at the cell region In order to reduce the SAS resistance at the cell region with low process cost, a method for fabricating a semiconductor device according to the present invention includes forming a protection layer on a semiconductor substrate on which a cell region and a periphera... | 10/17/2006 |
| 7122734 | Isoelectronic surfactant suppression of threading dislocations in metamorphic epitaxial layers A method of reducing propagation of threading dislocations into active areas of an optoelectronic device having a III–V material system includes growing a metamorphic buffer region in the presence of an isoelectronic surfactant. A first buffer layer may be lattice... | 10/17/2006 |
| 7084068 | Annealing furnace, manufacturing apparatus, annealing method and manufacturing method of electronic device An annealing furnace, includes a processing chamber configured to store a substrate; a susceptor located in the processing chamber so as to load the substrate and having an auxiliary heater for heating the substrate at 650° C. or less, the susceptor having a surfac... | 08/01/2006 |
| 7078329 | Method of manufacturing silicon carbide semiconductor device An insulating film (2) is formed on a semiconductor substrate (1) formed of silicon carbide. A contact hole (3) is formed in the insulating film (2) to expose a part of the upper surface of the semiconductor substrate (1). Then, ni... | 07/18/2006 |
| 7071042 | Method of fabricating silicon integrated circuit on glass A method of fabricating a silicon integrated circuit on a glass substrate includes preparing a glass substrate; fabricating a silicon layer on the glass substrate; implanting ions into the active areas of the silicon layer; covering the silicon layer with a heat pad... | 07/04/2006 |
| 7041577 | Process for manufacturing a substrate and associated substrate A process for producing a substrate is described. The process includes providing an assembly having a first layer weakly bonded to a temporary support at an interface therebetween. At least a portion of the first layer is selectively etched substantially to the inte... | 05/09/2006 |
| 7033961 | Epitaxy/substrate release layer The present invention relates to an epitaxial structure having one or more structural epitaxial layers, including a gallium nitride (GaN) layer, which is deposited on a substrate, and a method of growing the epitaxial structure, wherein the structural epitaxial laye... | 04/25/2006 |
| 7026258 | Method for making thin-film semiconductors based on I-III-VIcompounds, for photovoltaic applications The invention concerns a method for making thin-film CIGS which consists in: electrochemically depositing on a substrate a layer of stoichiometry close to CuInSe2; then rapidly annealing said layer from a light source with pulses of sufficient power to re... | 04/11/2006 |
| 7026229 | Athermal annealing with rapid thermal annealing system and method A method and system to achieve shallow junctions using Electromagnetic Induction Heating (EMIH) that can be preceded or followed by a low-temperature Rapid Thermal Annealing (RTA) process. The methods and systems can use, for example, RF or microwave frequencies to ... | 04/11/2006 |
| 7018941 | Post treatment of low k dielectric films A method of depositing a low dielectric constant film on a substrate and post-treating the low dielectric constant film is provided. The post-treatment includes rapidly heating the low dielectric constant film to a desired high temperature and then rapidly cooling t... | 03/28/2006 |
| 6992025 | Strained silicon on insulator from film transfer and relaxation by hydrogen implantation Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device ch... | 01/31/2006 |
| 6962884 | Monitoring low temperature rapid thermal anneal process using implanted wafers A method for processing integrated circuit devices. The method includes providing a monitor wafer, which comprising a silicon material. The method introduces a plurality of particles within a depth of the silicon material. The plurality of particles have a reduced a... | 11/08/2005 |
| 6960482 | Method of fabricating nitride semiconductor and method of fabricating semiconductor device A method of fabricating a nitride semiconductor includes the steps of forming a nitride semiconductor doped with a p-type impurity, treating the surface of the nitride semiconductor in an atmosphere containing active oxygen to remove carbon remaining on the surface ... | 11/01/2005 |
| 6960486 | Mid-IR microchip laser: ZnS:Cr2+ laser with saturable absorber material A method of fabrication of laser gain material and utilization of such media includes the steps of introducing a transitional metal, preferably Cr2+ thin film of controllable thickness on the ZnS crystal facets after crystal growth by means of pulse laser... | 11/01/2005 |
| 6946368 | Reduction of native oxide at germanium interface using hydrogen-based plasma A germanium substrate is positioned in a process chamber. A plasma is generated from a treatment gas that includes a flow of a hydrogen-containing gas. The plasma is provided to the process chamber to react with GeO2 in the germanium substrate. ... | 09/20/2005 |
| 6933158 | Method of monitoring anneal processes using scatterometry, and system for performing same The present invention is directed to several inventive methods of monitoring anneal processes performed on implant regions, and a system for accomplishing same. In one aspect, the method comprises forming a first plurality of implant regions in a semiconducting subs... | 08/23/2005 |
| 6913992 | Method of modifying interlayer adhesion Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on t... | 07/05/2005 |
| 6905983 | Apparatus and method for manufacturing semiconductor devices, and semiconductor device An apparatus of manufacturing a semiconductor device is disclosed which comprises at least one heat/light source opposing at least one major surface of a to-be-processed substrate, the heat/light source emitting light rays with a heating function onto the major surf... | 06/14/2005 |
| 6902870 | Patterning of dielectric with added layers of materials aside from photoresist for enhanced pattern transfer For patterning an opening through a patterned material, a coating material, a slow-etch material, and a photoresist material are deposited over the patterned material. The opening is patterned through the photoresist material, and the slow-etch material exposed thro... | 06/07/2005 |
| 6903032 | Method for preparing a semiconductor wafer surface A method for preparing a semiconductor wafer wherein rapid thermal annealing is conducted to smooth a free surface of a superficial zone that is supported by the wafer. The improvement includes treating the superficial zone before conducting the rapid thermal anneal... | 06/07/2005 |
| 6893894 | Method of manufacturing a compound semiconductor by heating a layered structure including rare earth transition metal A method of manufacturing a compound semiconductor includes the steps of forming a layered structure of dielectric layers including oxygen or sulfur, and an inter layer formed between the dielectric layers, including rare earth transition metal that is highly reacti... | 05/17/2005 |
| 6881658 | Process of and apparatus for heat-treating II-VI compound semiconductors and semiconductor heat-treated by the process A process of heat-treating II-VI compound semiconductors reduces the electrical resistivity without the decrease in crystallinity resulting from the increase in dislocation density. The process comprises the following steps:(a) placing at least one II-VI compound se... | 04/19/2005 |
| 6876017 | Polymer sacrificial light absorbing structure and method Method and structure for optimizing dual damascene patterning with polymeric dielectric materials are disclosed. Certain embodiments of the invention comprise polymeric sacrificial light absorbing materials (“polymer SLAM”) functionalized to have a controllable ... | 04/05/2005 |
| 6861340 | Method of heat-treating nitride compound semiconductor layer and method of producing semiconductor device A method of heat-treating a nitride compound semiconductor layer, comprising heating a nitride compound semiconductor layer doped with a p-type impurity at a temperature that is at least 200° C. but less than 400° C. for at least 100 minutes. ... | 03/01/2005 |
