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Behavior Modification Wristwatch
A wristwatch including a watch band and a watch body having an octagon shaped perimeter and being red in color and having the word STOP thereon to resemble a stop sign.
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| Number | Title | Issue Date |
| 8163658 | Multiple patterning using improved patternable low-k dielectric materials A method of double patterning a semiconductor structure with a single material which after patterning becomes a permanent part of the semiconductor structure. More specifically, a method to form a patterned semiconductor structure with small features is provided whi... | 04/24/2012 |
| 8153535 | Combinatorial plasma enhanced deposition techniques Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material... | 04/10/2012 |
| 8148273 | Combinatorial plasma enhanced deposition techniques Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material... | 04/03/2012 |
| 8129288 | Combinatorial plasma enhanced deposition techniques Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material... | 03/06/2012 |
| 8114783 | Silicon carbide semiconductor element, method of manufacturing the same, and silicon carbide device A silicon carbide semiconductor element and a manufacturing method thereof are disclosed in which a low contact resistance is attained between an electrode film and a wiring conductor element, and the wiring conductor element is hardly detached from the electrode fi... | 02/14/2012 |
| 8105955 | Integrated circuit system with carbon and non-carbon silicon An integrated circuit system includes a substrate, a carbon-containing silicon region over the substrate, a non-carbon-containing silicon region over the substrate, and a silicon-carbon region, including the non-carbon-containing silicon region and the carbon-contai... | 01/31/2012 |
| 8101527 | Dicing film having shrinkage release film and method for manufacturing semiconductor package using the same The present invention relates to a dicing film having an adhesive film for dicing a wafer and a die adhesive film, which are used for manufacturing a semiconductor package, and a method of manufacturing a semiconductor package using the same. More particularly, the ... | 01/24/2012 |
| 8043976 | Adhesion to copper and copper electromigration resistance The present invention relates to the improved adhesion between a patterned conductive metal layer, usually a copper layer, and a patterned barrier dielectric layer. The structure with the improved adhesion comprises an adhesion layer between a patterned barrier diel... | 10/25/2011 |
| 8026183 | Method of forming a resist pattern A lower-layer film to which a fluorine-doped polymer is added is formed on a film to be processed. The lower-layer film is baked. An intermediate film is formed on the lower-layer film. A resist film is formed on the intermediate film. The resist film is baked. A re... | 09/27/2011 |
| 8012885 | Manufacturing method of semiconductor device To provide a manufacturing method of a semiconductor device capable of performing a selective growth at a low temperature. A manufacturing method of a semiconductor device for placing in a processing chamber a substrate having at least a silicon surface and an insul... | 09/06/2011 |
| 7981808 | Method of forming a gate dielectric by in-situ plasma A method of forming a gate dielectric layer includes forming a first dielectric layer over a semiconductor substrate using a first plasma, performing a first in-situ plasma nitridation of the first dielectric layer to form a first nitrided dielectric layer, forming ... | 07/19/2011 |
| 7951726 | Organic/inorganic hybrid thin film passivation layer for blocking moisture/oxygen transmission and improving gas barrier property The present invention relates to an organic/inorganic hybrid thin film passivation layer comprising an organic polymer passivation layer prepared by a UV/ozone curing process and an inorganic thin film passivation layer for blocking moisture and oxygen transmission ... | 05/31/2011 |
| 7943529 | Passivation structure and fabricating method thereof A passivation structure and fabricating method thereof includes providing a chip having a main die region and a scribe line region defined thereon and a plurality of metal pads respectively positioned in the main die region and the scribe line region, forming a firs... | 05/17/2011 |
| 7935643 | Stress management for tensile films The formation of a gap-filling silicon oxide layer with reduced tendency towards cracking is described. The deposition involves the formation of a flowable silicon-containing layer which facilitates the filling of trenches. Subsequent processing at high substrate te... | 05/03/2011 |
| 7928016 | Method of manufacturing semiconductor device, and semiconductor device A method for manufacturing a semiconductor device is provided that can reduce warping of manufactured products after the formation of a final protective film. The method includes, in a semiconductor device having a semiconductor substrate provided with wiring and a ... | 04/19/2011 |
| 7902084 | Silicon dioxide deposition methods using at least ozone and TEOS as deposition precursors Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors... | 03/08/2011 |
| 7892983 | Substrate processing apparatus and producing method of semiconductor device Disclosed is a substrate processing apparatus, comprising a processing chamber, a holder to hold at least a plurality of product substrates, a heating member, a supplying member to alternately supply at least a first reactant and a second reactant, and a control uni... | 02/22/2011 |
| 7884030 | Gap-filling with uniform properties During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a... | 02/08/2011 |
| 7851378 | Method for growing Ge expitaxial layer on patterned structure with cyclic annealing A Ge epitaxial layer is grown on a silicon substrate with a patterned structure. Through a cyclic annealing, dislocation defects are confined. The present invention provides a method for manufacturing a high-quality Ge epitaxial layer with a low cost and a simple pr... | 12/14/2010 |
| 7851379 | Substrate processing method and substrate processing apparatus There are provided a substrate processing method and apparatus adapted to prevent deterioration of film thickness uniformity while maintaining the film forming rate. The substrate processing method comprises: (a) accommodating a plurality of substrates in a process ... | 12/14/2010 |
| 7851377 | Chemical vapor deposition process A chemical vapor deposition (CVD) method includes placing a semiconductor wafer into a reaction chamber; introducing a precursor into the reaction chamber; activating the precursor to a high-energy state using a non-direct plasma energy source; and reacting the prec... | 12/14/2010 |
| 7846850 | Method of fabricating insulation layer and method of fabricating semiconductor device using the same A method for fabricating an insulation layer includes forming an insulation layer over a nitride layer using a silicon source and a phosphorus source, wherein the insulation layer includes a first insulation layer contacting the nitride layer and a second insulation... | 12/07/2010 |
| 7842620 | Method for manufacturing semiconductor device using quadruple-layer laminate There is provided a laminate used as an underlayer layer for a photoresist in a lithography process of a semiconductor device and a method for manufacturing a semiconductor device by using the laminate. The method comprising: laminating each layer of an organic unde... | 11/30/2010 |
| 7816279 | Semiconductor device and method for manufacturing the same A semiconductor device includes a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first con... | 10/19/2010 |
| 7781349 | Method and system for optimizing a BARC stack In the present invention, a BARC stack comprising at least a first BARC layer and at least a second BARC layer is optimized for reducing substrate reflectivity in lithographic processing applications. The first BARC layer is positioned adjacent the resist layer, whi... | 08/24/2010 |
| 7767590 | Semiconductor device with spacer having batch and non-batch layers A semiconductor device including a gate stack located over a substrate and a spacer located over the substrate and adjacent the gate stack. The spacer includes a plurality of layers, wherein at least one of the plurality of layers is a batch layer and at least one o... | 08/03/2010 |
| 7737046 | Quantum dot array and production method therefor, and dot array element and production method therefor The present invention is a method of manufacturing a quantum dot array having a plurality of columnar parts including a quantum dot on a substrate, the method comprising the steps of obliquely vapor-depositing a material constituting a first barrier layer to become ... | 06/15/2010 |
| 7727903 | Method of forming strain-causing layer for MOS transistors and process for fabricating strained MOS transistors A method of forming a strain-causing layer for MOS transistors is provided, which is applied to a substrate having a plurality of gate structures of the MOS transistors thereon. A non-conformal stressed film that is thicker on the gate structures than between the ga... | 06/01/2010 |
| 7666799 | Epitaxial growth of relaxed silicon germanium layers A relaxed silicon germanium structure comprises a silicon buffer layer produced using a chemical vapor deposition process with an operational pressure greater than approximately 1 torr. The relaxed silicon germanium structure further comprises a silicon germanium la... | 02/23/2010 |
| 7629269 | High-k thin film grain size control A method including depositing a suspension of a colloid comprising an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic m... | 12/08/2009 |
| 7618900 | Semiconductor device and method of fabricating semiconductor device A semiconductor device may be fabricated according to a method that reduces stain difference of a passivation layer in the semiconductor device. The method may include forming top wiring patterns in a substrate, depositing a primary undoped silicate glass (USG) laye... | 11/17/2009 |
| 7576013 | Method of relieving wafer stress A method of relieving wafer stress is provided. A wafer is provided, wherein at least a dielectric layer has already formed over the wafer and the wafer has a first and a second area. At least no circuits are formed on the dielectric layer within the first area. The... | 08/18/2009 |
| 7514372 | Epitaxial growth of relaxed silicon germanium layers A relaxed silicon germanium structure comprises a silicon buffer layer produced using a chemical vapor deposition process with an operational pressure greater than approximately 1 torr. The relaxed silicon germanium structure further comprises a silicon germanium la... | 04/07/2009 |
| 7485583 | Method for fabricating superlattice semiconductor structure using chemical vapor deposition The invention provides a method for fabricating a superlattice semiconductor structure capable of achieving excellent interfacial properties and uniformity. For the superlattice semiconductor structure according to the invention, a substrate is mounted on a suscepto... | 02/03/2009 |
| 7482285 | Dual epitaxial layer for high voltage vertical conduction power MOSFET devices The epitaxial silicon junction receiving layer of a power semiconductor device is formed of upper and lower layers. The lower layer has a resistivity of more than that of the upper layer and a thickness of more than that of the upper layer. The total thickness of th... | 01/27/2009 |
| 7465676 | Method for forming dielectric film to improve adhesion of low-k film A semiconductor structure having improved adhesion between a low-k dielectric layer and the underlying layer and a method for forming the same are provided. The semiconductor substrate includes a dielectric layer over a semiconductor substrate, an adhesion layer on ... | 12/16/2008 |
| 7442653 | Inter-metal dielectric of semiconductor device and manufacturing method thereof including plasma treating a plasma enhanced fluorosilicate glass An exemplary manufacturing method of an inter-metal dielectric of a semiconductor device according to an embodiment of the present invention includes forming a first silicon-rich oxide (SRO) layer on a silicon substrate provided with or otherwise having a copper lin... | 10/28/2008 |
| 7439191 | Deposition of silicon layers for active matrix liquid crystal display (AMLCD) applications A method of silicon layer deposition using a cyclical deposition process. The cyclical deposition process comprises alternately adsorbing a silicon-containing precursor and a reducing gas on a substrate structure. Thin film transistors, such as for example a bottom-... | 10/21/2008 |
| 7439154 | Method of fabricating interconnect structure A method for fabricating an interconnect structure is described. A substrate with a conductive part thereon is provided, a first porous low-k layer is formed on the substrate, and then a first UV-curing step is conducted. A damascene structure is formed in the first... | 10/21/2008 |
| 7436067 | Methods for forming conductive structures and structures regarding same A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g., ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain bou... | 10/14/2008 |
