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| Number | Title | Issue Date |
| 8163656 | Process for adjusting the size and shape of nanostructures In accordance with the invention, a lateral dimension of a microscale device on a substrate is reduced or adjusted by the steps of providing the device with a soft or softened exposed surface; placing a guiding plate adjacent the soft or softened exposed surface; an... | 04/24/2012 |
| 8163657 | Process for adjusting the size and shape of nanostructures In accordance with the invention, a lateral dimension of a microscale device on a substrate is reduced or adjusted by the steps of providing the device with a soft or softened exposed surface; placing a guiding plate adjacent the soft or softened exposed surface; an... | 04/24/2012 |
| 7700498 | Self-repair and enhancement of nanostructures by liquification under guiding conditions In accordance with the invention, the structure (10A, 10B) of a patterned nanoscale or near nanoscale device (“nanostructure”) is repaired and/or enhanced by liquifying the patterned device in the presence of appropriate guiding conditions for a pe... | 04/20/2010 |
| 7618899 | Method of patterning a matrix into a substrate via multiple, line-and-space, sacrificial, hard mask layers Methods of fabricating a semiconductor integrated circuit device are disclosed. The methods of fabricating a semiconductor integrated circuit device include forming a hard mask layer on a base layer, forming a line sacrificial hard mask layer on the hard mask layer ... | 11/17/2009 |
| 7446054 | Method for manufacturing semiconductor device It is an object of the present invention to provide a method for manufacturing a semiconductor device in which prevention of disconnection due to a step caused by a surface shape before film formation, control of increase in the cost in forming an insulating film ov... | 11/04/2008 |
| 7416985 | Semiconductor device having a multilayer interconnection structure and fabrication method thereof A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench formed in the first interlayer insulation film and having a sidewall s... | 08/26/2008 |
| 7384862 | Method for fabricating semiconductor device and display device It is an object of the present invention to alleviate unevenness due to an opening for making a contact with the lower layer even when the opening has a large diameter (1 μm or more). Thus, it is a further object of the invention to reduce defects caused by the une... | 06/10/2008 |
| 7368393 | Chemical oxide removal of plasma damaged SiCOH low k dielectrics A method for removing damages of a dual damascene structure after plasma etching is disclosed. The method comprises the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged r... | 05/06/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7354779 | Topography compensated film application methods Methods for applying topographically compensated film in a semiconductor wafer fabrication process are disclosed. The processes include premapping a surface of a wafer so as to determine the local topography (e.g., z-height) of the wafer and then applying a variable... | 04/08/2008 |
| 7338911 | Method for etching and for forming a contact hole using thereof A method for forming a structure formed by etching which is typified by a contact hole in the semiconductor and a method for manufacturing a display device using the structure. The etching method includes at least, forming an organic mask having a first opening port... | 03/04/2008 |
| 7325180 | System and method to test integrated circuits on a wafer A system to test integrated circuits on a wafer may include a transceiver formed on the wafer. The system may also include an antenna system couplable to the transceiver. The transceiver may be formed in one of a scribe line on the wafer, a chip on the wafer or on a... | 01/29/2008 |
| 7309269 | Method of fabricating light-emitting device and apparatus for manufacturing light-emitting device In this embodiment, an interval distance between a desposition source holder 17 and an object on which deposition is performed (substrate 13) is reduced to 30 cm or less, preferably 20 cm or less, more preferably 5 to 15 cm, and a deposition source hol... | 12/18/2007 |
| 7301168 | Organic light emitting diode display and manufacturing method with partition and emission regions to improve emission characteristics An organic light emitting display according to an embodiment of the invention includes: a substrate; a first electrode disposed on the substrate; a first partition disposed on the first electrode and having an opening exposing the first electrode; a second partition... | 11/27/2007 |
| 7297640 | Method for reducing argon diffusion from high density plasma films A two-step high density plasma-CVD process is described wherein the argon content in the film is controlled by using two different argon concentrations in the argon/silane/oxygen gas mixture used for generating the high density plasma. The first step deposition uses... | 11/20/2007 |
| 7282456 | Self-repair and enhancement of nanostructures by liquification under guiding conditions In accordance with the invention, the structure of a patterned nanoscale or near nanoscale device (“nanostructure”) is repaired and/or enhanced by liquifying the patterned device in the presence of appropriate guiding conditions for a period of time and then per... | 10/16/2007 |
| 7274452 | Alignment apparatus An alignment apparatus 10 comprises a table 11 which is provided rotatably in a plane, and equipped with a loading plane 12A capable of sucking a wafer W, a shift mechanism 30 that moves the table 11 in the X- and Y-axis directions... | 09/25/2007 |
| 7270886 | Spin-on glass composition and method of forming silicon oxide layer in semiconductor manufacturing process using the same A spin-on glass (SOG) composition and a method of forming a silicon oxide layer utilizing the SOG composition are disclosed. The method includes coating on a semiconductor substrate having a surface discontinuity, an SOG composition containing polysilazane having a ... | 09/18/2007 |
| 7255772 | High pressure processing chamber for semiconductor substrate A high pressure chamber comprises a chamber housing, a platen, and a mechanical drive mechanism. The chamber housing comprises a first sealing surface. The platen comprises a region for holding the semiconductor substrate and a second sealing surface. The mechanical... | 08/14/2007 |
| 7247584 | System and method for selectively increasing surface temperature of an object A system and method for selectively increasing the thermal effect of a radiant energy source to the surface of an object relative to the substrate is described in the context of rapid thermal processing of semiconductor wafers, and apparatus produced therefrom. A ra... | 07/24/2007 |
| 7235345 | Agent for forming coating for narrowing patterns and method for forming fine pattern using the same It is disclosed an over-coating agent for forming fine patterns which is applied to cover a substrate having photoresist patterns thereon and allowed to shrink under heat so that the spacing between the adjacent photoresist patterns is lessened, further characterize... | 06/26/2007 |
| 7229914 | Wiring layer structure for ferroelectric capacitor Wiring layers through that come into direct contact with an electrode of a ferroelectric capacitor provide a wiring layer structure configured so that the characteristic of the ferroelectric substance is not degraded by production of a reducing agent. One of coating... | 06/12/2007 |
| 7208416 | Method of treating a structured surface The invention provides a simple method of treating a structured surface comprising a higher surface in a first region and a lower surface in the second region. A plurality of layers is deposited on said surface wherein a lower layer exhibits a higher polishing rate ... | 04/24/2007 |
| 7199062 | Method for forming a resist film on a substrate having non-uniform topography A preferred embodiment of the invention provides a method of spin coating a liquid, such as a resist, onto a surface of a substrate. An embodiment of the invention comprises dispensing a liquid onto the surface; spinning the substrate at a first rotational velocity ... | 04/03/2007 |
| 7192891 | Method for forming a silicon oxide layer using spin-on glass A method is provided for forming silicon oxide layers during the processing of semiconductor devices by applying a SOG layer including polysilazane to a substrate and then substantially converting the SOG layer to a silicon oxide layer using an oxidant solution. The... | 03/20/2007 |
| 7189659 | Method for fabricating a semiconductor device A method for fabricating a semiconductor device comprises the step of depositing an insulation film 32a with a first pressure set in a deposition chamber; the step of gradually decreasing the pressure in the deposition chamber to a second pressure whic... | 03/13/2007 |
| 7189499 | Method of forming fine patterns It is disclosed a method of forming fine patterns comprising: covering a substrate having photoresist patterns with an over-coating agent for forming fine patterns, removing the unwanted over-coating agent that has been deposited on the edge portions and/or the back... | 03/13/2007 |
| 7183172 | Method of forming silicon-on-insulator (SOI) semiconductor substrate and SOI semiconductor substrate formed thereby A method of forming an SOI semiconductor substrate and the SOI semiconductor substrate formed thereby, is provided. The method includes forming sequentially buried oxide, diffusion barrier and SOI layers on a semiconductor substrate. The diffusion barrier layer is f... | 02/27/2007 |
| 7157331 | Ultraviolet blocking layer Methods and apparatuses are disclosed relating to blocking ultraviolet electromagnetic radiation from a semiconductor. Ultraviolet electromagnetic radiation, such as ultraviolet electromagnetic radiation generated by a plasma process, which may otherwise damage a se... | 01/02/2007 |
| 7153731 | Method of forming a field effect transistor with halo implant regions A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed withi... | 12/26/2006 |
| 7141483 | Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill A method of filling a gap defined by adjacent raised features on a substrate includes providing a flow of a silicon-containing processing gas to a chamber housing the substrate and providing a flow of an oxidizing gas to the chamber. The method also includes deposit... | 11/28/2006 |
| 7115468 | Semiconductor device and method for fabricating the same A semiconductor device and a fabricating method for the same are disclosed, in which when forming a capacitor sacrificial film pattern, even if a misalignment occurs, the degradation of the dielectric property due to a direct contact between the contact plug and the... | 10/03/2006 |
| 7105927 | Structure of dummy pattern in semiconductor device Disclosed herein is a dummy pattern structure of a semiconductor device. The dummy pattern structure may include daughter dummy patterns respectively formed at places corresponding to vertexes of polygons in regions where metal wirings are not formed in an interlaye... | 09/12/2006 |
| 7105460 | Nitrogen-free dielectric anti-reflective coating and hardmask Methods are provided for depositing a dielectric material. The dielectric material may be used for an anti-reflective coating or as a hardmask. In one aspect, a method is provided for processing a substrate including introducing a processing gas comprising a silane-... | 09/12/2006 |
| 7087518 | Method of passivating and/or removing contaminants on a low-k dielectric/copper surface One aspect of the invention relates to a method of removing contaminants from a low-k film. The method involves forming a sacrificial layer over the contaminated film. The contaminants combine with the sacrificial layer and are removed by etching away the sacrificia... | 08/08/2006 |
| 7087506 | Method of forming freestanding semiconductor layer A method of providing a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel on a monocrystalline base structure. A conformal polycrystalline semiconductor layer is then form... | 08/08/2006 |
| 7078296 | Self-aligned trench MOSFETs and methods for making the same Self-aligned trench MOSFETs and methods for manufacturing the same are disclosed. By having a self-aligned structure, the number of MOSFETS per unit area—the cell density—is increased, making the MOSFETs cheaper to produce. The self-aligned structure for the MOS... | 07/18/2006 |
| 7070659 | System for filling openings in semiconductor products Explosive forces are used to fill interconnect material into trenches, via holes and other openings in semiconductor products. The interconnect material may be formed of metal. The metal may be heated prior to the force filling step. The explosive forces may be gene... | 07/04/2006 |
| 7060197 | Micromechanical mass flow sensor and method for the production thereof In a mass flow sensor having a layered structure on the upper side of a silicon substrate (1), and having at least one heating element (8) patterned out of a conductive layer in the layered structure, thermal insulation between the heating element (... | 06/13/2006 |
| 7060623 | Method of deforming a pattern and semiconductor device formed by utilizing deformed pattern A method of deforming a pattern comprising the steps of: forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper groove, wherein the re-flow stopper groove extends outside the selecte... | 06/13/2006 |
