Celebrity Inventors
Glam girl Heddy Lamar may have used her good looks to good effect on the silver screen, but she put her smarts to better use as an inventor. During World War II, she co-patented a frequency-switching system for torpedo guidance that was considered years ahead of its time.
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| Number | Title | Issue Date |
| 8163655 | Method for forming a sacrificial sandwich structure The present disclosure provides a method for making a semiconductor device. The method includes forming a first material layer on a substrate; forming a second material layer on the first material layer; forming a sacrificial layer on the second material layer; form... | 04/24/2012 |
| 7759257 | Precision synthesis of quantum dot nanostructures for fluorescent and optoelectronic devices Methods are disclosed generally directed to design and synthesis of quantum dot nanoparticles having improved uniformity and size. In a preferred embodiment, a release layer is deposited on a semiconductor wafer. A heterostructure is grown on the release layer using... | 07/20/2010 |
| 7687408 | Method for integrated circuit fabrication using pitch multiplication Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the ... | 03/30/2010 |
| 7618898 | Method and apparatus for forming contact hole A method of forming a contact hole in an insulating film coating amorphous Si having an irregular surface formed on an insulating substrate, for connecting the amorphous Si to a conductor film formed on the insulating film, including: etching the insulating film usi... | 11/17/2009 |
| 7442652 | Method for removing contamination and method for fabricating semiconductor device A method for removing contamination on a semiconductor substrate is disclosed. The contamination contains at least one element belonging to one of 3A group, 3B group and 4A group of long-period form of periodic system of elements. The method comprises first and seco... | 10/28/2008 |
| 7435683 | Apparatus and method for selectively recessing spacers on multi-gate devices Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed. ... | 10/14/2008 |
| 7429534 | Etching a nitride-based heterostructure An improved solution for producing nitride-based heterostructure(s), heterostructure device(s), integrated circuit(s) and/or Micro-Electro-Mechanical System(s) is provided. A nitride-based etch stop layer that includes Indium (In) is included in a heterostructure. A... | 09/30/2008 |
| 7410901 | Submicron device fabrication A method for fabricating substrate material to include trenches and unreleased beams with submicron dimensions includes etching a first oxide layer on the substrate to define a first set of voids in the first oxide layer to expose the substrate. A second oxide layer... | 08/12/2008 |
| 7371695 | Use of TEOS oxides in integrated circuit fabrication processes A method for manufacturing a low temperature removable silicon dioxide hard mask for patterning and etching is provided, wherein tetra-ethyl-ortho-silane (TEOS) is used to deposit a silicon dioxide hard mask. ... | 05/13/2008 |
| 7348260 | Method for forming a relaxed or pseudo-relaxed useful layer on a substrate A method for forming a relaxed or pseudo-relaxed useful layer on a substrate is described. The method includes growing a strained semiconductor layer on a donor substrate, bonding a receiver substrate to the strained semiconductor layer by a vitreous layer of a mate... | 03/25/2008 |
| 7348259 | Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers A method of fabricating a semiconductor structure. According to one aspect of the invention, on a first semiconductor substrate, a first compositionally graded Si1-xGex buffer is deposited where the Ge composition x is increasing from about zer... | 03/25/2008 |
| 7344997 | Semiconductor substrate, semiconductor device, method for manufacturing semiconductor substrate and method for manufacturing semiconductor device A semiconductor substrate comprising a semiconductor base, a dielectric layer formed in at least a part of an area on the semiconductor base, and a single crystal semiconductor layers having mutually different film thicknesses, disposed on the dielectric layer and f... | 03/18/2008 |
| 7338908 | Method for fabrication of semiconductor interconnect structure with reduced capacitance, leakage current, and improved breakdown voltage An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that ... | 03/04/2008 |
| 7319076 | Low resistance T-shaped ridge structure A method and apparatus to provide a low resistance interconnect. A void is defined in the sacrificial layer that is proximate to an active layer. An overgrowth layer is formed in the void and over portions of the sacrificial layer adjacent to the void. A ridge secti... | 01/15/2008 |
| 7303995 | Method for reducing dimensions between patterns on a photoresist A semiconductor manufacturing method that includes providing a substrate, providing a layer of material over the substrate, providing a layer of photoresist over the material layer, patterning and defining the photoresist layer, depositing a layer of polymer over th... | 12/04/2007 |
| 7303933 | Process of manufacturing a semiconductor device A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In.... | 12/04/2007 |
| 7301180 | Structure and method for a high-speed semiconductor device having a Ge channel layer The invention provides semiconductor structure comprising a strained Ge channel layer, and a gate dielectric disposed over the strained Ge channel layer. In one aspect of the invention, a strained Ge channel MOSFET is provided. The strained Ge channel MOSFET include... | 11/27/2007 |
| 7268065 | Methods of manufacturing metal-silicide features A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the se... | 09/11/2007 |
| 7259091 | Technique for forming a passivation layer prior to depositing a barrier layer in a copper metallization layer By performing a wet chemical process after etching a via, contaminations may be removed and a thin passivation layer may be formed that may then be readily removed in a subsequent sputter etch process for forming a barrier/adhesion layer. In a particular embodiment,... | 08/21/2007 |
| 7250359 | Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer.... | 07/31/2007 |
| 7244958 | Integration of strained Ge into advanced CMOS technology A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial deposit... | 07/17/2007 |
| 7238620 | System and method for providing a uniform oxide layer over a laser trimmed fuse with a differential wet etch stop technique A system and method is disclosed for using a differential wet etch stop technique to provide a uniform oxide layer over a metal layer in a laser trimmed fuse. A layer of boron doped oxide with a slow etch rate is placed over the metal layer. A layer of phosphorus do... | 07/03/2007 |
| 7227176 | Etch stop layer system A semiconductor structure including a uniform etch-stop layer. The uniform etch stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×1019 boron atoms/cm3. A method for forming a semicon... | 06/05/2007 |
| 7217978 | SRAM memories and microprocessors having logic portions implemented in high-performance silicon substrates and SRAM array portions having field effect transistors with linked bodies and method for making same The present invention generally concerns fabrication methods and device architectures for use in memory circuits, and more particularly concerns hybrid silicon-on-insulator (SOI) and bulk architectures for use in memory circuits. Once aspect of the invention concern... | 05/15/2007 |
| 7202139 | MOSFET device with a strained channel An ultra thin MOSFET device structure located on an insulator layer, and a method of forming the ultra thin MOSFET device structure featuring a strained silicon channel located on the underlying insulator layer, has been developed. After epitaxial growth of a semico... | 04/10/2007 |
| 7198970 | Technique for perfecting the active regions of wide bandgap semiconductor nitride devices This invention pertains to electronic/optoelectronic devices with reduced extended defects and to a method for making it. The method includes the steps of depositing a dielectric thin film mask material on a semiconductor substrate surface; patterning the mask mater... | 04/03/2007 |
| 7195987 | Methods of forming CMOS integrated circuit devices and substrates having buried silicon germanium layers therein CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-x... | 03/27/2007 |
| 7195993 | Methods of fabricating gallium nitride semiconductor layers by lateral growth into trenches A gallium nitride layer is laterally grown into a trench in the gallium nitride layer, to thereby form a lateral gallium nitride semiconductor layer. At least one microelectronic device may then be formed in the lateral gallium nitride semiconductor layer. Dislocati... | 03/27/2007 |
| 7192910 | Cleaning solutions and etchants and methods for using same Composition for cleaning or etching a semiconductor substrate and method for using the same. The composition may include a fluorine-containing compound as an active agent such as a quaternary ammonium fluoride, a quaternary phosphonium fluoride, sulfonium fluoride, ... | 03/20/2007 |
| 7189628 | Fabrication of trenches with multiple depths on the same substrate Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches an... | 03/13/2007 |
| 7172975 | Process for the wet chemical treatment of semiconductor wafers A process for the wet chemical treatment of semiconductor wafers, in which the semiconductor wafers are treated with treatment liquids, has the semiconductor wafers firstly treated with an aqueous HF solution, then treated with an aqueous O3 solution and ... | 02/06/2007 |
| 7157331 | Ultraviolet blocking layer Methods and apparatuses are disclosed relating to blocking ultraviolet electromagnetic radiation from a semiconductor. Ultraviolet electromagnetic radiation, such as ultraviolet electromagnetic radiation generated by a plasma process, which may otherwise damage a se... | 01/02/2007 |
| 7122095 | Methods for forming an assembly for transfer of a useful layer Methods for forming an assembly for transfer of a useful layer are described. In an embodiment, the method includes forming a useful layer on a first support having an interface therebetween, and a residual material on a portion of the first support to form the asse... | 10/17/2006 |
| 7119006 | Via formation for damascene metal conductors in an integrated circuit A method of fabricating an integrated circuit, having copper metallization formed by a dual damascene process, is disclosed. A layered insulator structure is formed over a first conductor (22), within which a second conductor (40) is formed to contact ... | 10/10/2006 |
| 7087534 | Semiconductor substrate cleaning Methods for removing titanium-containing layers from a substrate surface where those titanium-containing layers are formed by chemical vapor deposition (CVD) techniques. Titanium-containing layers, such as titanium or titanium nitride, formed by CVD are removed from... | 08/08/2006 |
| 7088590 | Soldermask opening to prevent delamination A multilayer circuit board includes a base layer, a conductive layer and a soldermask. The soldermask layer has two sets of openings. One of the openings are vent openings, that expose the base layer to provide ventilation so that gases may escape during processing.... | 08/08/2006 |
| 7084460 | Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate materi... | 08/01/2006 |
| 7071116 | Semiconductor device and method for manufacturing same The temperature of the sputtering process for forming the Ti film is selected to a temperature within a range of from 200 degree C. to 225 degree C. to provide stable film quality against oxidization (step 11). The irradiation with ultraviolet is conducted be... | 07/04/2006 |
| 7067389 | Method for manufacturing semiconductor device The present invention discloses a method for forming an element isolation film of a semiconductor device, comprising the steps of: sequentially forming a pad oxide film, a pad nitride film and a mask oxide film on a semiconductor substrate on which a first region fo... | 06/27/2006 |
| 7060632 | Methods for fabricating strained layers on semiconductor substrates Methods for fabricating multi-layer semiconductor structures including strained material layers using a minimum number of process tools and under conditions optimized for each layer. Certain regions of the strained material layers are kept free of impurities that ca... | 06/13/2006 |
