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| Number | Title | Issue Date |
| 7816274 | Methods for normalizing strain in a semiconductor device The electrical performance enhancing effects of inducing strain in semiconductor devices is made substantially uniform across a substrate having a varying population density of device components by selectively spacing apart the strain-inducing structures from the ef... | 10/19/2010 |
| 7666797 | Methods for forming semiconductor constructions, and methods for selectively etching silicon nitride relative to conductive material The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containe... | 02/23/2010 |
| 7442650 | Methods of manufacturing semiconductor structures using RIE process A method for etching on a semiconductors at the back end of line using reactive ion etching. The method comprises reduced pressure atmosphere and a mixture of gases at a specific flow rate ratio during plasma generation and etching. Plasma generation is induced by a... | 10/28/2008 |
| 7435688 | Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first ma... | 10/14/2008 |
| 7435683 | Apparatus and method for selectively recessing spacers on multi-gate devices Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed. ... | 10/14/2008 |
| 7425277 | Method for hard mask CD trim Broadly speaking, methods and an apparatus are provided for removing an inorganic material from a substrate. More specifically, the methods provide for removing the inorganic material from the substrate through exposure to a high density plasma generated using an in... | 09/16/2008 |
| 7422936 | Facilitating removal of sacrificial layers via implantation to form replacement metal gates Replacement metal gates may be formed by removing a polysilicon layer from a gate structure. The gate structure may be formed by patterning the polysilicon layer and depositing a spacer layer over the gate structure such that the spacer layer has a first polish rate... | 09/09/2008 |
| 7402513 | Method for forming interlayer insulation film It is an object of the present invention to provide a method for forming an interlayer insulation film suppressing the occurrence of voids in the interlayer insulation film. A method for forming an interlayer insulation film of the present invention, comprisi... | 07/22/2008 |
| 7393791 | Etching method, method of fabricating metal film structure, and etching structure There is provided an etching method in which a protective film existing in an etching-destined region of a substrate structure is removed by means of ICP-RIE to form an exposure region of the principal surface of the substrate. The substrate structure comprises a su... | 07/01/2008 |
| 7358595 | Method for manufacturing MOS transistor Disclosed is a method for fabricating a MOS transistor. The present method includes forming a buffer layer pattern including nitrogen on the semiconductor substrate; forming a gate insulating layer and a gate electrode on the exposed substrate surface; forming a LDD... | 04/15/2008 |
| 7326358 | Plasma processing method and apparatus, and storage medium A plasma processing method performs a plasma processing on a substrate mounted on a mounting table installed in an airtight processing chamber, the mounting table having a smaller size than the substrate. The substrate having a surface, on which a resist mark is for... | 02/05/2008 |
| 7316785 | Methods and apparatus for the optimization of etch resistance in a plasma processing system In a plasma processing system, including a plasma processing chamber, a method of optimizing the etch resistance of a substrate material is described. The method includes flowing pre-coat gas mixture into the plasma processing chamber, wherein the pre-coat gas mixtu... | 01/08/2008 |
| 7309656 | Method for forming step channel of semiconductor device A method for forming a step channel of a semiconductor device is disclosed. The method for forming a step channel of a semiconductor device comprises forming a hard mask layer pattern defining a step channel region on a semiconductor substrate, forming a spacer on a... | 12/18/2007 |
| RE39895 | Semiconductor integrated circuit arrangement fabrication method To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited t... | 10/23/2007 |
| 7276450 | Etching processes using CFfor silicon dioxide and CFfor titanium nitride Methods of etching a dielectric layer and a cap layer over a conductor to expose the conductor are disclosed. In one embodiment, the methods include the use of a silicon dioxide (SiO2) etching chemistry including octafluorocyclobutane (C4F... | 10/02/2007 |
| 7265026 | Method of forming a shallow trench isolation structure in a semiconductor device An isolation method in a semiconductor device is disclosed. The example method sequentially forms a pad oxide layer and a pad nitride layer on a semiconductor substrate, patterns the pad nitride and oxide layers to form an opening exposing a portion of the substrate... | 09/04/2007 |
| 7256134 | Selective etching of carbon-doped low-k dielectrics The present invention includes a process for selectively etching a low-k dielectric material formed on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a fluorine-rich fluorocarbon or hydrofluorocarbon gas, a nitrogen-c... | 08/14/2007 |
| 7244644 | Undercut and residual spacer prevention for dual stressed layers Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer ov... | 07/17/2007 |
| 7211197 | Etching method and plasma processing method A processing gas constituted of CH2F2, O2 and Ar is introduced into a processing chamber 102 of a plasma processing apparatus 100. The flow rate ratio of the constituents of the processing gas is set at CH2F | 05/01/2007 |
| 7208419 | Method for fabricating semiconductor device The present invention relates to a method for fabricating a semiconductor device. The method comprises the steps of: forming a gate line on a semiconductor substrate; forming a buffer layer and a spacer nitride film on the entire surface of the substrate including t... | 04/24/2007 |
| 7196343 | Optical element, lithographic apparatus including such an optical element, device manufacturing method, and device manufactured thereby An optical element including an anti-reflection (AR) coating is configured to reflect Extreme-Ultra-Violet (EUV) radiation only. ... | 03/27/2007 |
| 7192894 | High performance CMOS transistors using PMD liner stress A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nit... | 03/20/2007 |
| 7172960 | Multi-layer film stack for extinction of substrate reflections during patterning A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus compris... | 02/06/2007 |
| 7166232 | Method for producing a solid body including a microstructure According to a method for producing a solid body (1) including a microstructure (2), the surface of a substrate (3) is provided with a masking layer (6) that is impermeable to a substance to be applied. The substance is then incorporated ... | 01/23/2007 |
| 7153778 | Methods of forming openings, and methods of forming container capacitors A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking lay... | 12/26/2006 |
| 7148143 | Semiconductor device having a fully silicided gate electrode and method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a silicided gate electrode (150) loca... | 12/12/2006 |
| 7141460 | Method of forming trenches in a substrate by etching and trimming both hard mask and a photosensitive layers A process is described for transferring a photoresist pattern into a substrate. In one embodiment a stack comprised of a top photoresist layer, a middle ARC layer, and a bottom hardmask is formed over a gate electrode layer. A line in the photoresist pattern is anis... | 11/28/2006 |
| 7119006 | Via formation for damascene metal conductors in an integrated circuit A method of fabricating an integrated circuit, having copper metallization formed by a dual damascene process, is disclosed. A layered insulator structure is formed over a first conductor (22), within which a second conductor (40) is formed to contact ... | 10/10/2006 |
| 7115450 | Approach to improve line end shortening including simultaneous trimming of photosensitive layer and hardmask A process is described for transferring a photoresist pattern into a substrate. In one embodiment a stack comprised of a top photoresist layer, a middle ARC layer, and a bottom hardmask is formed over a gate electrode layer. A line in the photoresist pattern is anis... | 10/03/2006 |
| 7084072 | Method of manufacturing semiconductor device Disclosed is a method of manufacturing a semiconductor device. The method includes the steps of forming a gate in a cell region and a peripheral region of a substrate, depositing a buffer oxide layer on the gate and the substrate, annealing a resultant structure of ... | 08/01/2006 |
| 7064075 | Method for manufacturing semiconductor electronics devices A method is described for manufacturing electronic semiconductor devices comprising the steps of depositing in sequence a layer of hydrophobic material and a “deep UV” photo-resist layer on a semiconductor substrate, selectively removing the “deep UV” photo-... | 06/20/2006 |
| 7060629 | Etch of silicon nitride selective to silicon and silicon dioxide useful during the formation of a semiconductor device A method for etching silicon nitride selective to silicon dioxide and silicon (polycrystalline silicon or monocrystalline silicon) comprises the use of oxygen along with an additional etchant of either CHF3 or CH2F2. Flow rates, powe... | 06/13/2006 |
| 7049244 | Method for enhancing silicon dioxide to silicon nitride selectivity A process for controlling the plasma etch of a silicon dioxide layer at a high etch rate and high selectivity with respect to silicon nitride, particularly in a multilayer structure, by (1) maintaining various portions of the etch chamber at elevated temperatures, a... | 05/23/2006 |
| 7045408 | Integrated circuit with improved channel stress properties and a method for making it An integrated circuit is described that comprises a PMOS transistor and an NMOS transistor that are formed on a semiconductor substrate. A silicate glass layer is formed on only the PMOS transistor or the NMOS transistor; and an etch stop layer is formed on the sili... | 05/16/2006 |
| 7045464 | Via reactive ion etching process Methods of etching a dielectric layer and a cap layer over a conductor level to open a via to the conductor. The methods include the provision of tetrafluoro methane (CF4) in a photoresist strip. In addition, the methods may provide an increased amount of... | 05/16/2006 |
| 7041567 | Isolation structure for trench capacitors and fabrication method thereof This invention relates to a method for self-aligned fabricating an isolation structure of a trench capacitor. The method takes two steps to etch the substrate for forming the shallow trench of the isolation structure, wherein the conductive layer and the collar oxid... | 05/09/2006 |
| 7018944 | Apparatus and method for nanoscale pattern generation A method and apparatus that produces highly ordered, nanosized particle arrays on various substrates. These regular arrays may be used as masks to deposit and grow other nanoscale materials. ... | 03/28/2006 |
| 7005380 | Simultaneous formation of device and backside contacts on wafers having a buried insulator layer A semiconductor device manufacturing method is provided where a device structure is formed on top of a wafer that comprises a backside semiconductor substrate, a buried insulator layer and a top semiconductor layer. Then, an etch stop layer is formed upon the wafer ... | 02/28/2006 |
| 6974989 | Structure and method for protecting memory cells from UV radiation damage and UV radiation-induced charging during backend processing According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The structure further comprises a first interlayer dielectric layer situated over the at least one memory ce... | 12/13/2005 |
| 6967170 | Methods of forming silicon nitride spacers, and methods of forming dielectric sidewall spacers The invention includes a method of patterning a material over a semiconductive substrate, comprising: a) forming a layer of first material against a second material and over the substrate, the substrate comprising a surface having a center and an edge; b) first etch... | 11/22/2005 |
