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Pizza Pie With Concentric Rings of Crust
A pizza mold for forming a plurality of concentric raised ridges of dough (i.e., crust) on the surface of a pizza pie.
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| Number | Title | Issue Date |
| 7704892 | Semiconductor device having local interconnection layer and etch stopper pattern for preventing leakage of current A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor... | 04/27/2010 |
| 7402529 | Method of applying cladding material on conductive lines of MRAM devices A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive mater... | 07/22/2008 |
| 7250323 | Methods of making energy conversion devices with a substantially contiguous depletion regions A method of making an energy conversion device includes forming a plurality of pores within a substrate and forming a junction region within each of the plurality of pores. Each of the junction regions has a depletion region and each of the plurality of pores define... | 07/31/2007 |
| 7195965 | Premature breakdown in submicron device geometries The concept of the present invention describes a semiconductor device with a junction 504 between a lightly doped region 501 and a heavily doped region 502, wherein the junction has an elongated portion 504a and curved portions ... | 03/27/2007 |
| 6992342 | Magnetic memory device having a non-volatile magnetic section and manufacturing thereof A magnetic memory device, in which a tunnel magneto resistance element that establishes a connection between a write word line (first interconnection) and a bit line (second interconnection) is provided within a region in which the write word line and the bit line c... | 01/31/2006 |
| 6767835 | Method of making a shaped gate electrode structure, and device comprising same In one illustrative embodiment, the method comprises forming a gate insulation layer above a substrate, forming a layer of polysilicon above the gate insulation layer, implanting a dopant material into the layer of polysilicon, forming an undoped layer of polysilico... | 07/27/2004 |
| 6642148 | RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral dimension is formed over the semiconductor substrate. The se... | 11/04/2003 |
| 6642158 | Photo-thermal induced diffusion Formation of a mixed-material composition through diffusion using photo-thermal energy. The diffusion may be used to create electrically conductive traces. The diffusion may take place between material layers on one of a package substrate, semiconductor s... | 11/04/2003 |
| 6211090 | Method of fabricating flux concentrating layer for use with magnetoresistive random access memories A method of fabricating a flux concentrator for use in magnetic memory devices including the steps of providing at least one magnetic memory bit (10) and forming proximate thereto a material stack defining a copper (Cu) damascene bit line (56) including a... | 04/03/2001 |
| 6127237 | Etching end point detecting method based on junction current measurement and etching apparatus A pn junction is formed at a to-be-etched depth in an etching region of a semiconductor body and a reverse bias voltage is applied to the pn junction to form a depletion layer. Then, the semiconductor body is etched while monitoring the reverse bias curre... | 10/03/2000 |
| 6107208 | Nitride etch using N2 /Ar/CHF3 chemistry In one embodiment, the present invention relates to a method of etching silicon nitride disposed over a copper containing layer by etching at least a portion of the silicon nitride using a nitride etch gas mixture comprising from about 5 sccm to about 15 ... | 08/22/2000 |
| 5858875 | Integrated circuits with borderless vias A method of forming interconnecting layers in a semiconductor device whereby even if a via is misaligned with a metal line, a portion of the via not enclosed and capped by the metal is enclosed and capped by an etch stop spacer. The foundation layer inclu... | 01/12/1999 |
| 5242533 | Method of structuring a semiconductor chip Processes are proposed for structuring monocrystalline semiconductor substrates provided with a basic doping, in particular silicon substrates with a (100) or (110) crystal orientation. In this process, at least one main surface of the semiconductor subst... | 09/07/1993 |
| 5129982 | Selective electrochemical etching A method of selectively etching a body of a semiconductor material, such as single crystalline silicon, having regions of n-type and p-type conductivity to remove at least a portion of the n-type region. The body is placed in an etching solution of an etc... | 07/14/1992 |
| 5129981 | Method of selectively etching silicon The present invention relates to a method of forming thin bodies of a semiconductor material, such as single crystalline silicon, by selectively etching away a portion of the body until a body of the desired thicknes is obtained. The body includes a p-n j... | 07/14/1992 |
| 5116457 | Semiconductor transducer or actuator utilizing corrugated supports A semiconductor transducer or acutator is disclosed. The transducer and actuator each include a deflecting member with corrugations producing increased vertical travel which is a linear function of applied force. An accurate and easily controlled method t... | 05/26/1992 |
| 4635343 | Method of manufacturing GaAs semiconductor device A method of manufacturing a GaAs semiconductor device of an E/D construction having a GaAs/AlGaAs heterojunction and utilizing two-dimensional electron gas, which includes the steps of forming a heterojunction semiconductor substrate and etching a portion... | 01/13/1987 |
