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| Number | Title | Issue Date |
| 7989357 | Method of patterning semiconductor structure and structure thereof Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-... | 08/02/2011 |
| 7919414 | Method for forming fine patterns in semiconductor device A method for forming fine patterns in a semiconductor device includes forming an etch stop layer and a sacrificial layer over an etch target layer, forming photoresist patterns over the sacrificial layer, etching the sacrificial layer by using the photoresist patter... | 04/05/2011 |
| 7825034 | Method of fabricating openings and contact holes A substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer is then patterned to form a plurality of openings exposing the etch stop layer. A dielectric thin film is subsequently formed to cover... | 11/02/2010 |
| 7799698 | Deposition-selective etch-deposition process for dielectric film gapfill A deposition/etching/deposition process is provided for filling a gap in a surface of a substrate. A liner is formed over the substrate so that distinctive reaction products are formed when it is exposed to a chemical etchant. The detection of such reaction products... | 09/21/2010 |
| 7776753 | Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation A method of fabricating a semiconductor device includes the steps of forming (or providing) a series of layers formed on a substrate, the layers including a first plurality of layers including an n-type ohmic contact layer, a p-type modulation doped quantum well str... | 08/17/2010 |
| 7767587 | Method of forming an interconnection structure in a organosilicate glass having a porous layer with higher carbon content located between two lower carbon content non-porous layers Interconnect structures possessing a non-porous (dense) low-k organosilicate glass (OSG) film utilizing a porous low-k OSG film as an etch stop layer or a porous low-k OSG film using a non-porous OSG film as a hardmask for use in semiconductor devices are provided h... | 08/03/2010 |
| 7759256 | Micro-electro-mechanical system device and method for making same According to the present invention, a method for making a micro-electro-mechanical system (MEMS) device comprises: providing a substrate with devices and interconnection formed thereon, the substrate having a to-be-etched region; depositing and patterning an etch st... | 07/20/2010 |
| 7691754 | Method for removing photoresist layer and method of forming opening A method for removing a photoresist layer is provided. The method is suitable for a dielectric layer, wherein the dielectric layer has a patterned photoresist layer formed thereon and a metal silicide layer disposed thereunder and there is an etching stop layer disp... | 04/06/2010 |
| 7691753 | Deposition-selective etch-deposition process for dielectric film gapfill A deposition/etching/deposition process is provided for filling a gap in a surface of a substrate. A liner is formed over the substrate so that distinctive reaction products are formed when it is exposed to a chemical etchant. The detection of such reaction products... | 04/06/2010 |
| 7659211 | Method and apparatus for fabricating a memory device with a dielectric etch stop layer The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as DRAM or SRAM, various layers are deposited to form structures, such as PMOS ... | 02/09/2010 |
| 7635650 | Prevention of plasma induced damage arising from etching of crack stop trenches in multi-layered low-k semiconductor devices A method of fabricating a semiconductor device begins by forming a lower interconnection dielectric on a substrate and forming at least one active or passive device in the lower interconnection dielectric. An etch stop layer is formed on the lower interconnection di... | 12/22/2009 |
| 7608546 | Method for fabricating a semiconductor device A method for fabricating a semiconductor device includes forming an etch target layer over a substrate that includes a cell region and a peripheral region. A first hard mask layer, a second hard mask layer, and an anti-reflective coating layer are formed over the et... | 10/27/2009 |
| 7598180 | Semiconductor process for removing defects due to edge chips of a semiconductor wafer and semiconductor device fabricated thereby A method for removing defects due to edge chips of a semiconductor wafer is disclosed. This method includes forming a molding layer over a semiconductor wafer. The molding layer is patterned to form a plurality of storage node holes, where the plurality of storage n... | 10/06/2009 |
| 7576011 | Method of forming contact plug in semiconductor A method of forming a contact plug in a semiconductor device includes the steps of forming a plurality of select lines and a plurality of word lines on a semiconductor substrate; forming a first etching stop layer on the select lines and the word lines; forming a se... | 08/18/2009 |
| 7572738 | Crack stop trenches in multi-layered low-k semiconductor devices A method is provided for fabricating a semiconductor device. The method begins by forming on a substrate an interconnect stack layer that includes a plurality of layers with interconnecting metal overlying the substrate. After forming the interconnect stack layer, a... | 08/11/2009 |
| 7557046 | Systems and methods for interconnect metallization using a stop-etch layer Systems and methods for single lithography step interconnection metallization using a stop-etch layer are described. A method comprises depositing a stop-etch layer over a semiconductor device, depositing an interconnect metallization material over the stop-etch lay... | 07/07/2009 |
| 7442651 | Plasma etching method An etching technique capable of applying etching at high selectivity to a transition metal element-containing electrode material layer which is formed on or above a dielectric material layer made of a high-dielectric-constant or “high-k” insulator is provided. T... | 10/28/2008 |
| 7429534 | Etching a nitride-based heterostructure An improved solution for producing nitride-based heterostructure(s), heterostructure device(s), integrated circuit(s) and/or Micro-Electro-Mechanical System(s) is provided. A nitride-based etch stop layer that includes Indium (In) is included in a heterostructure. A... | 09/30/2008 |
| 7425512 | Method for etching a substrate and a device formed using the method The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substra... | 09/16/2008 |
| 7422985 | Method for reducing dielectric overetch using a dielectric etch stop at a planar surface A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. In a preferred embodiment, the conductive or semiconductor features are pillars forming vertically oriented diodes. A second dielectric material, diffe... | 09/09/2008 |
| 7422954 | Method for fabricating a capacitor structure A capacitor structure is described, including a substrate, a first metal layer in the substrate, an etching stop layer on the substrate having therein an opening that exposes a portion of the first metal layer, a connection layer on the portion of the first metal la... | 09/09/2008 |
| 7393714 | Method of manufacturing external force detection sensor A method of manufacturing an external force detection sensor in which a sensor element is formed by through-hole dry etching of an element substrate, and an electrically conductive material is used as an etching stop layer during the dry etching. ... | 07/01/2008 |
| 7365009 | Structure of metal interconnect and fabrication method thereof A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric condu... | 04/29/2008 |
| 7359113 | Semiconductor optical amplifier having a non-uniform injection current density A semiconductor optical amplifier (SOA) with efficient current injection is described. Injection current density is controlled to be higher in some areas and lower in others to provide, e.g., improved saturation power and/or noise figure. Controlled injection curren... | 04/15/2008 |
| 7348231 | Methods of fabricating semiconductor devices having insulating layers with differing compressive stresses Methods of fabricating semiconductor devices are provided. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate and the PMOS transistor is positioned on a PMOS region of the substr... | 03/25/2008 |
| 7344995 | Method for preparing a structure with high aspect ratio The present invention discloses a method for preparing a structure with high aspect ratio, which can be a trench or a conductor. A first mask is formed on a substrate, and a first etching process is performed to remove the substrate uncovered by the first mask to fo... | 03/18/2008 |
| 7329599 | Method for fabricating a semiconductor device Methods are provided for semiconductor devices having low contact resistance. The method in accordance with one embodiment of the invention comprises forming an insulating layer overlying a semiconductor substrate, the semiconductor substrate having a device region ... | 02/12/2008 |
| 7329953 | Structure for reducing leakage currents and high contact resistance for embedded memory and method for making same A method for fabricating an insulating layer having contact openings of varying depths for logic/DRAM circuits is achieved using a single mask and etch step. After forming stacked or trench capacitors, a planar insulating layer is formed. Contact openings are etched... | 02/12/2008 |
| 7329610 | Method of high selectivity SAC etching A method for SAC etching is provided involving a) etching a Si wafer having a nitride present thereon with a first etching gas containing a first perfluorocarbon and carbon monoxide, and b) etching the resultant Si wafer having an initially etched nitride photoresis... | 02/12/2008 |
| 7323407 | Method of fabricating dual damascene interconnections of microelectronic device using diffusion barrier layer against base material Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during processing are provided. The methods include the steps of: filling a ... | 01/29/2008 |
| 7312144 | Unitary interconnection structures integral with a dielectric layer and fabrication methods thereof An interconnection structure is provided by forming a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in th... | 12/25/2007 |
| 7309656 | Method for forming step channel of semiconductor device A method for forming a step channel of a semiconductor device is disclosed. The method for forming a step channel of a semiconductor device comprises forming a hard mask layer pattern defining a step channel region on a semiconductor substrate, forming a spacer on a... | 12/18/2007 |
| 7291562 | Method to form topography in a deposited layer above a substrate In the present invention a dummy structure is formed in a first deposited layer in order to create topography, generally a raised area, in a deposited layer formed above and later than the first deposited layer. This topography may be advantageous in later steps. In... | 11/06/2007 |
| 7288482 | Silicon nitride etching methods Methods of etching silicon nitride material, and more particularly, etching nitride selective to silicon dioxide or silicide, are disclosed. The methods include exposing a substrate having silicon nitride thereon to a plasma including at least one fluorohydrocarbon ... | 10/30/2007 |
| 7282447 | Method for an integrated circuit contact A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect... | 10/16/2007 |
| 7273566 | Gas compositions Processes, etchants, and apparatus useful for etching an insulating oxide layer of a substrate without damaging underlying nitride features or field oxide regions. The processes exhibit good selectivity to both nitrides and field oxides. Integrated circuits produced... | 09/25/2007 |
| 7262137 | Dry etching process for compound semiconductors Accordingly, this invention relates to an dry etching process for semiconductor wafers. More particularly, the present invention discloses a dry etching process including a halogen etchant (24) and a nitrogen gas (28) that selectively etches a compound... | 08/28/2007 |
| 7256134 | Selective etching of carbon-doped low-k dielectrics The present invention includes a process for selectively etching a low-k dielectric material formed on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a fluorine-rich fluorocarbon or hydrofluorocarbon gas, a nitrogen-c... | 08/14/2007 |
| 7256137 | Method of forming contact plug on silicide structure A method of manufacturing a semiconductor device is provided comprising the steps of: (a) forming a semiconductor element on a substrate, the semiconductor element having at least one nickel silicide contact region, a first etch stop layer formed over the element an... | 08/14/2007 |
| 7250370 | Two step post-deposition treatment of ILD layer for a lower dielectric constant and improved mechanical properties A method of lowering the dielectric constant of an organosilicon low k dielectric layer while improving the hardness and thermal stability is provided. A deposited layer of carbon doped oxide, HSQ, or MSQ is cured and treated with a He plasma which improves hardness... | 07/31/2007 |
