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| Number | Title | Issue Date |
| 8043973 | Mask overhang reduction or elimination after substrate etch A method of forming IC devices includes providing a substrate and forming a patterned masking layer including at least one masked region having at least one masking layer, and a feature region bounded by the masking layer. Etching forms an etched feature in the subs... | 10/25/2011 |
| 8003545 | Method of forming an electronic device including forming features within a mask and a selective removal process A method of forming an electronic device can include forming a patterned mask layer overlying a underlying layer such that the mask layer has a first feature, a second feature, and a third feature, and the first feature is between the second feature and the third fe... | 08/23/2011 |
| 7875556 | Precursors for CVD silicon carbo-nitride and silicon nitride films Classes of liquid aminosilanes have been found which allow for the production of silicon carbo-nitride films of the general formula SixCyNz. These aminosilanes, in contrast, to some of the precursors employed heretofore, are liquid a... | 01/25/2011 |
| 7863197 | Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification A method for fabricating the semiconductor structure include a semiconductor substrate having a cross-section hourglass shaped channel region. A stress imparting layer is located adjacent the channel region. The hourglass shape may provide for enhanced vertical tens... | 01/04/2011 |
| 7759255 | Semiconductor device and method for manufacturing the same In one embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a to-be-removed layer on a semiconductor substrate; forming a semiconductor layer on the to-be-removed layer; forming a trench that passes through the sem... | 07/20/2010 |
| 7674720 | Stacking fault reduction in epitaxially grown silicon Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove... | 03/09/2010 |
| 7629264 | Structure and method for hybrid tungsten copper metal contact The present invention in one embodiment provides a method of forming an interconnect comprising, providing a interlevel dielectric layer atop a substrate, the interlevel dielectric layer including at least one tungsten (W) stud extending from an upper surface of the... | 12/08/2009 |
| 7547641 | Super hybrid SOI CMOS devices The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orienta... | 06/16/2009 |
| 7517807 | Methods for fabricating semiconductor structures A method for fabricating a semiconductor structure includes forming a carbon masking layer on a semiconductor layer, forming a protective layer on the carbon masking layer. The method further includes forming an opening in the protective layer and the carbon masking... | 04/14/2009 |
| 7465674 | Manufacturing method of semiconductor device An object of the present invention is to provide a method for manufacturing a semiconductor device with high reliability, at low cost, in which an element forming layer having a thin film transistor and the like provided over a substrate is peeled from the substrate... | 12/16/2008 |
| 7442603 | Self-aligned structure and method for confining a melting point in a resistor random access memory A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying... | 10/28/2008 |
| 7439093 | Method of making a MEMS device containing a cavity with isotropic etch followed by anisotropic etch A method of making an etch structure in a substrate involves the steps of providing a mask on a substrate with a pattern that leaves at least one opening leaving the substrate in direct contact with the ambient, performing an isotropic or quasi-isotropic etch throug... | 10/21/2008 |
| 7435685 | Method of forming a low-K dual damascene interconnect structure A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is the... | 10/14/2008 |
| 7431853 | Selective etching of oxides from substrates A method and system for release etching a micro-electrical-mechanical-systems (MEMS) device from a substrate. In one aspect, the invention is a method comprising (a) supporting at least one substrate having a sacrificial oxide and a non-sacrificial material in a pro... | 10/07/2008 |
| 7375037 | Fabrication method for semiconductor integrated circuit device To improve the shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. The... | 05/20/2008 |
| 7355254 | Pinning layer for low resistivity N-type source drain ohmic contacts A system or apparatus including an N-type transistor structure including a gate electrode formed on a substrate and source and drain regions formed in the substrate; a contact to the source region; and a pinning layer disposed between the source region and the first... | 04/08/2008 |
| 7332399 | Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor in which film thicknesses can be accurately controlled A method of manufacturing semiconductor substrates. After supporting layers are provided on side walls of grooves formed in a semiconductor substrate, grooves that expose a second semiconductor layer are formed. Etching gas or etching liquid is brought in contact wi... | 02/19/2008 |
| 7329613 | Structure and method for forming semiconductor wiring levels using atomic layer deposition A method for forming a conductive wire structure for a semiconductor device includes defining a mandrel on a substrate, forming a conductive wire material on the mandrel by atomic layer deposition, and forming a liner material around the conductive wire material by ... | 02/12/2008 |
| 7320908 | Methods of forming semiconductor devices having buried oxide patterns Methods for forming semiconductor devices are provided. A semiconductor substrate is etched such that the semiconductor substrate defines a trench and a preliminary active pattern. The trench has a floor and a sidewall. An insulating layer is provided on the floor a... | 01/22/2008 |
| RE40007 | In-situ strip process for polysilicon etching in deep sub-micron technology A new method of patterning the polysilicon layer in the manufacture of an integrated circuit device has been achieved. A polysilicon layer is provided overlying a semiconductor substrate. The polysilicon layer may overlie a gate oxide layer and thereby comprise the ... | 01/22/2008 |
| 7311850 | Method of forming patterned thin film and method of fabricating micro device In a method of forming a patterned thin film, first, an etching stopper film and a film to be patterned are formed in this order on a base layer. Next, a patterned first film is formed on the film to be patterned. Next, a second film is formed over an entire surface... | 12/25/2007 |
| 7282447 | Method for an integrated circuit contact A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect... | 10/16/2007 |
| 7279341 | Method for fabricating a flux concentrating system for use in a magnetoelectronics device A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) o... | 10/09/2007 |
| 7276453 | Methods for forming an undercut region and electronic devices incorporating the same An electronic device having a substrate structure having an undercut region is provided and further included is a method for forming an undercut region of a substrate structure. The method includes forming a patterned protective layer over a first electrode. The met... | 10/02/2007 |
| 7271448 | Multiple gate field effect transistor structure A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substan... | 09/18/2007 |
| 7256077 | Method for removing a semiconductor layer A method of forming a semiconductor device includes forming a first layer over a semiconductor substrate and forming a second layer over the first layer. The second layer includes silicon and has an etch selectivity to the second layer that is greater than approxima... | 08/14/2007 |
| 7253086 | Recessed drain extensions in transistor device A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate st... | 08/07/2007 |
| 7241684 | Method of forming metal wiring of semiconductor device A method for forming a metal wiring of a semiconductor device. The method includes forming an etch stop layer on a semiconductor substrate, forming a first inter metal dielectric on the etch stop layer, and forming a second inter metal dielectric on the first inter ... | 07/10/2007 |
| 7241693 | Processing method for protection of backside of a wafer A temporal protection layer is employed to a wafer backside for use of micro-electro-mechanical systems (MEMS). The formation of the temporal protection layer prevents the wafer backside from scratch in process of transferring system for IC manufacturers. With regar... | 07/10/2007 |
| 7235478 | Polymer spacer formation A polymer spacer material may increase the dimensions of the patterned photoresist that is used as a mask to etch the layers below the photoresist, which in turn translates into smaller dimensions etched into the underlying materials. This allows for the formation o... | 06/26/2007 |
| 7235493 | Low-k dielectric process for multilevel interconnection using mircocavity engineering during electric circuit manufacture One embodiment of a method for forming a low-k dielectric for a semiconductor device assembly comprises forming a silicon dioxide layer, then forming a patterned masking layer such as silicon nitride on the silicon dioxide. Using the patterned nitride layer as a pat... | 06/26/2007 |
| 7230264 | Semiconductor transistor having structural elements of differing materials A transistor is formed using a semiconductor substrate and forming a control electrode overlying the semiconductor substrate. A first current electrode is formed within the semiconductor substrate and adjacent the control electrode. The first current electrode has a... | 06/12/2007 |
| 7226821 | Flip chip die assembly using thin flexible substrates Apparatus and methods for flattening thin substrate surfaces by stretching thin flexible substrates to which ICs can be bonded. Various embodiments beneficially maintain the substrate flatness during the assembly process through singulation. According to one embodim... | 06/05/2007 |
| 7202179 | Method of forming at least one thin film device This invention provides a method of forming at least one thin film device, such as for example a thin film transistor. The method includes providing a substrate and depositing a plurality of thin film device layers upon the substrate. An imprinted 3D template struct... | 04/10/2007 |
| 7195927 | Process for making magnetic memory structures having different-sized memory cell layers An exemplary method for making a memory structure having different-sized memory cell layers comprises forming at least two layers of ferromagnetic materials, forming at least one mask layer above the ferromagnetic materials, patterning the at least one mask layer, e... | 03/27/2007 |
| 7183217 | Dry-etching method A dry-etching method using an apparatus where a wafer is placed on either of a pair of opposed electrodes provided in an etching chamber, and high-frequency power is supplied to both the opposed electrodes to effect a plasma etching. The plasma etching uses a gas co... | 02/27/2007 |
| 7179708 | Process for fabricating non-volatile memory by tilt-angle ion implantation A process for fabricating non-volatile memory by tilt-angle ion implantation comprises essentially the steps of implanting sideling within a nitride dielectric layer heterogeneous elements such as, for example, Ge, Si, N2, O2, and the like, for forming traps capable... | 02/20/2007 |
| 7163865 | Method of forming transistor having recess channel in semiconductor memory, and structure thereof Embodiments of the invention include sequentially forming a pad oxide film and a mask film on a semiconductor substrate, and then forming an opening for partially exposing the pad oxide film. An undercut region is formed using the mask film as an etch mask, exposing... | 01/16/2007 |
| 7138341 | Process for making a memory structure An exemplary method for making a memory structure comprises forming a first hard mask layer, forming at least one mask layer above the first hard mask layer, patterning the at least one mask layer, etching the at least one mask layer to form an opening having a firs... | 11/21/2006 |
| 7132349 | Methods of forming integrated circuits structures including epitaxial silicon layers in active regions An integrated circuit structure can include an isolation structure that electrically isolates an active region of an integrated circuit substrate from adjacent active regions and an insulation layer that extends from the isolation structure to beneath the active reg... | 11/07/2006 |
