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| Number | Title | Issue Date |
| 8143170 | Manufacturing method of semiconductor device A single crystal semiconductor layer is provided over a base substrate with a second insulating film, a first conductive film, and a first insulating film interposed therebetween; an impurity element having one conductivity type is selectively added to the single cr... | 03/27/2012 |
| 7981806 | Method for forming trench and method for fabricating semiconductor device using the same A method for forming a trench includes providing a substrate, and forming the trench in the substrate using a gas containing chlorine (Cl2) gas as a main etch gas and SiFX gas as an additive gas, wherein a sidewall of the trench has a substanti... | 07/19/2011 |
| 7915176 | Device comprising a field of tips used in biotechnology applications A method for manufacturing a device including a field of micrometric tips, including forming a polycrystalline layer on a support; performing an anisotropic plasma etching of all or part of the polycrystalline layer by using a gas mixture including chlorine and heli... | 03/29/2011 |
| 7884026 | Method of fabricating dual damascene structure A semiconductor wafer includes a substrate, a conductive layer, a dielectric layer having a via, a hard mask defined a trench pattern, and a sacrificial layer. Then a sequential of etching processes is performed upon the semiconductor wafer in a chamber to form a tr... | 02/08/2011 |
| 7713882 | Patterning method for a semiconductor substrate A patterning method for a semiconductor substrate is disclosed. A substrate is provided and a stack structure is laid thereon. The stack layer includes at least a target layer and a pad layer sequentially formed on the substrate. Follow by a lithography process, whe... | 05/11/2010 |
| 7691752 | Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed thereby Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a (100) plane to f... | 04/06/2010 |
| 7629262 | Method of forming a lower electrode of a capacitor In an embodiment, a method of forming a lower electrode of a capacitor in a semiconductor memory device includes etching a mold oxide layer to have at a cylindrical structure, resulting in an electrode with increased surface area. The cylindrical structure may have ... | 12/08/2009 |
| 7592264 | Process for removing material from substrates A method of removing materials, and preferably photoresist, from a substrate comprises dispensing a liquid sulfuric acid composition comprising sulfuric acid and/or its desiccating species and precursors and having a water/sulfuric acid molar ratio of no greater tha... | 09/22/2009 |
| 7569489 | High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfac... | 08/04/2009 |
| 7528075 | Self-masking defect removing method A method for removing defects from a semiconductor surface is disclosed. The surface of the semiconductor is first coated with a protective layer, which is later thinned to selectively reveal portions of the protruding defects. The defects are then removed by etchin... | 05/05/2009 |
| 7456112 | Method of fabricating micro-needle array A method of fabricating a micro-needle array is provided. The method of fabricating a micro-needle array having a substrate having a first surface and a second surface spaced in a predetermined interval apart from the first surface, includes patterning on the first ... | 11/25/2008 |
| 7435685 | Method of forming a low-K dual damascene interconnect structure A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is the... | 10/14/2008 |
| 7432213 | Electrical connection pattern in an electronic panel A connector layout for arranging a plurality of parallel electrical connectors between two electronic devices. Each connector has a strip connected to a bump pad. Each strip has a certain required strip width and each bump pad has a certain required pad width. Each ... | 10/07/2008 |
| 7429534 | Etching a nitride-based heterostructure An improved solution for producing nitride-based heterostructure(s), heterostructure device(s), integrated circuit(s) and/or Micro-Electro-Mechanical System(s) is provided. A nitride-based etch stop layer that includes Indium (In) is included in a heterostructure. A... | 09/30/2008 |
| 7427569 | Metal etching process and rework method thereof A metal etching process is described. A substrate having a dielectric layer thereon is provided. An aluminum-copper alloy layer is formed on the dielectric layer. A hard mask layer is formed on the aluminum-copper alloy layer. A patterned photoresist layer is formed... | 09/23/2008 |
| 7419915 | Laser assisted chemical etching method for release microscale and nanoscale devices A method using an etchant and a laser for localized precise heating enables precise etching and release of MEMS devices with improved process control while expanding the number of materials used to make MEMS, including silicon-dioxide patterned films buried in and s... | 09/02/2008 |
| 7410907 | Fabricating integrated devices using embedded masks A method of fabricating a device using a multi-layered wafer that has an embedded etch mask adapted to map a desired device structure onto an adjacent (poly)silicon layer. Due to the presence of the embedded mask, it becomes possible to delay the etching that forms ... | 08/12/2008 |
| 7381640 | Method of forming metal line and contact plug of flash memory device A method of forming a metal line and a contact plug of a flash memory device, wherein if first, second, and third etch processes are performed on an anti-reflection film and regions (a region in which a contact plug through which a gate is exposed is formed/a region... | 06/03/2008 |
| 7344997 | Semiconductor substrate, semiconductor device, method for manufacturing semiconductor substrate and method for manufacturing semiconductor device A semiconductor substrate comprising a semiconductor base, a dielectric layer formed in at least a part of an area on the semiconductor base, and a single crystal semiconductor layers having mutually different film thicknesses, disposed on the dielectric layer and f... | 03/18/2008 |
| 7344994 | Multiple layer etch stop and etching method A process for etching semiconductor substrates using a deep reactive ion etching process to produce through holes or slots (hereinafter “slots”) in the substrates. The process includes applying a first layer to a back side of a substrate as a first etch stop mat... | 03/18/2008 |
| 7341943 | Post etch copper cleaning using dry plasma A method for post-etch copper cleaning uses a hydrogen plasma with a trace gas additive constituting about 3-10 percent of the plasma by volume to clean a copper surface exposed by etching. The trace gas may be atomic nitrogen or other species having an atomic mass ... | 03/11/2008 |
| 7309654 | Technique for reducing etch damage during the formation of vias and trenches in interlayer dielectrics By performing a first common etch process for forming a via opening and a delineation trench or open area in a metallization layer with different removal rates, the etch front in the delineation trench or open area may be delayed, thereby significantly reducing the ... | 12/18/2007 |
| 7291282 | Method of fabricating a mold for imprinting a structure The present invention provides a method of fabricating an imprint mold for molding a structure. The method includes directing a first and a second flux for forming a first material and a second material, respectively, to a substrate to form a layered structure havin... | 11/06/2007 |
| 7282455 | Method of producing a diffraction grating In an embodiment, a method of producing a diffraction grating comprises steps of: forming, on a man surface of a first member, a first mask having a plurality of resist patterns arranged at a Bragg diffraction period; etching the first member by use of the first mas... | 10/16/2007 |
| 7282447 | Method for an integrated circuit contact A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect... | 10/16/2007 |
| 7250247 | Photolithographic structures using multiple anti-reflecting coatings A method for fabricating an integrated circuit using a photo-lithographic process includes the steps of placing at least two anti-reflective coating layers between a reflective surface and another material. The indices of refraction, absorptions, and thicknesses of ... | 07/31/2007 |
| 7214626 | Etching process for decreasing mask defect The present invention provides an etching process for decreasing mask defect. The process comprises providing a substrate, and sequentially forming a thin film layer, a mask, and a photoresist on the surface of the substrate. Then the photoresist is trimmed by a bro... | 05/08/2007 |
| 7208396 | Permanent adherence of the back end of a wafer to an electrical component or sub-assembly A plurality of successive layers are firmly adhered to one another and to a wafer surface and an electrical component or sub-assembly even when the wafer surface is not even and the layers are bent. The wafer surface is initially cleaned by an ion bombardment of an ... | 04/24/2007 |
| 7205244 | Patterning substrates employing multi-film layers defining etch-differential interfaces The present invention features a method of patterning a substrate that includes forming, on the substrate, a multi-layer film with a surface, an etch rate interface and an etch-differential interface. The etch-differential interface is defined between the etch rate ... | 04/17/2007 |
| 7203872 | Cache based physical layer self test A software self test engine is executed from a cache of a processor. The software self test engine is executed using an execution engine of the processor to perform a physical layer self test. The physical layer self test is performed by transmitting a test vector f... | 04/10/2007 |
| 7198981 | Vacuum sealed surface acoustic wave pressure sensor A vacuum sealed SAW pressure sensor is disclosed herein, which includes a sensing element configured as a SAW device (e.g., SAW resonator or SAW delay line) supported by a thin diaphragm. The substrate material can be implemented as a quartz wafer (i.e., a “base... | 04/03/2007 |
| 7166232 | Method for producing a solid body including a microstructure According to a method for producing a solid body (1) including a microstructure (2), the surface of a substrate (3) is provided with a masking layer (6) that is impermeable to a substance to be applied. The substance is then incorporated ... | 01/23/2007 |
| 7153710 | Etching method, method of manufacturing semiconductor device, and semiconductor device In an etching method, an etching amount is controlled on the basis of the number of times an etching process is performed under the condition that an etching amount is determined independently of an etching time. Accordingly, the etching can be performed in step-by-... | 12/26/2006 |
| 7141275 | Imprinting lithography using the liquid/solid transition of metals and their alloys A method is provided for imprinting a pattern having nanoscale features from a mold into the patternable layer on a substrate. The method comprises: providing the mold; forming the patternable layer on the substrate; and imprinting the mold into the patternable laye... | 11/28/2006 |
| 7135360 | Liquid crystal display device and method of fabricating the same A liquid crystal display device includes a plurality of gate lines and data lines on a first substrate defining a plurality of pixel regions, a thin film transistor within the pixel regions, a pixel electrode within the pixel regions, and at least one TiOx layer pro... | 11/14/2006 |
| 7109125 | Selective fabrication of high capacitance density areas in a low dielectric constant material Method for selective fabrication of high capacitance density areas in a low dielectric constant material and related structure are disclosed. In one embodiment, a first area of a dielectric layer is covered, for example with photoresist, while a second area of the d... | 09/19/2006 |
| 7105457 | Semiconductor device manufacturing method and apparatus used in the semiconductor device manufacturing method A semiconductor device manufacturing method includes forming circuit devices and a plurality of electrode pads within a semiconductor chip formation region. The method also includes forming, on the main surface of the semiconductor wafer, an insulating film which ex... | 09/12/2006 |
| 7105436 | Method for in-line monitoring of via/contact holes etch process based on test structures in semiconductor wafer manufacturing A method for in-line monitoring of via/contact etching process based on a test structure is described. The test structure is comprised of via/contact holes of different sizes and densities in a layout such that, for a certain process, the microloading or RIE lag ind... | 09/12/2006 |
| 7098143 | Etching method using an at least semi-solid media An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove meta... | 08/29/2006 |
| 7074718 | Method of fabricating a semiconductor device having a buried and enlarged contact hole According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patter... | 07/11/2006 |
