Did You Know...
...that "patent leather" got its name because the process of applying the polished black finish to leather was once patented?
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8187981 | Substrate processing method, substrate processing system, and computer-readable storage medium A substrate processing method includes preparing a substrate having a low-k interlayer dielectric film as a to-be-etched film and a photoresist film, formed on the low-k interlayer insulating film, serving as an etching mask with a predetermined circuit pattern; etc... | 05/29/2012 |
| 8093156 | Method for manufacturing semiconductor device To provide a method for manufacturing a semiconductor device, which the method is capable of efficient mass production of high-performance semiconductor devices by, upon manufacture of a semiconductor device, eliminating unwanted features (e.g., side lobes) created ... | 01/10/2012 |
| 8088691 | Selective etch chemistries for forming high aspect ratio features and associated structures An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from ... | 01/03/2012 |
| 8043972 | Adsorption based material removal process Methods for accurate and conformal removal of atomic layers of materials make use of the self-limiting nature of adsorption of at least one reactant on the substrate surface. In certain embodiments, a first reactant is introduced to the substrate in step (a) and is ... | 10/25/2011 |
| 8008212 | Fabrication methods for integration CMOS and BJT devices Fabrication methods for integrating CMOS and BJT devices are presented. A semiconductor substrate having a first region and a second region are provided, wherein the first region includes a CMOS device, and the second region includes a BJT device. A dielectric layer... | 08/30/2011 |
| 7943524 | Method of etching and etching apparatus Silicon oxide film having, as a sublayer, a silicon nitride film layer serving as a protective film layer for 5 gate formed on silicon substrate is etched by introducing a processing gas including a gaseous mixture containing at least C4F6, Ar,... | 05/17/2011 |
| 7902080 | Deposition-plasma cure cycle process to enhance film quality of silicon dioxide Methods of filling a gap on a substrate with silicon oxide are described. The methods may include the steps of introducing an organo-silicon precursor and an oxygen precursor to a deposition chamber, reacting the precursors to form a first silicon oxide layer in the... | 03/08/2011 |
| 7879733 | Method for manufacturing semiconductor device free from layer-lifting between insulating layers A method for manufacturing a semiconductor device free from layer lifting between insulating layers. The method comprises forming a silicon oxide layer on a semiconductor substrate, forming a silicon rich oxynitride (SRON) layer as an etching mask on the silicon oxi... | 02/01/2011 |
| 7846848 | Cluster tool with integrated metrology chamber for transparent substrates The embodiments of the invention relate to a method and apparatus for measuring the etch depth in a semiconductor photomask processing system. In one embodiment, a method for etching a substrate includes etching a transparent substrate in an etch chamber coupled to ... | 12/07/2010 |
| 7838434 | Method of plasma etching of high-K dielectric materials A method of etching high dielectric constant materials using a halogen gas, a reducing gas and an etch rate control gas chemistry. ... | 11/23/2010 |
| 7786019 | Multi-step photomask etching with chlorine for uniformity control Methods for etching quartz are provided herein. In one embodiment, a method of etching quartz includes providing a film stack on a substrate support disposed in a processing chamber, the film stack having a quartz layer partially exposed through a patterned layer; a... | 08/31/2010 |
| 7745343 | Method for fabricating semiconductor device with fuse element A method for fabricating a semiconductor device with a fuse element includes providing a semiconductor structure with a fuse element formed over a first device region thereof. A first interlayer dielectric layer, an etching stop layer and a second interlayer dielect... | 06/29/2010 |
| 7682986 | Ultra-high aspect ratio dielectric etch A method for etching an ultra high aspect ratio feature in a dielectric layer through a carbon based mask is provided. The dielectric layer is selectively etched with respect to the carbon based mask, wherein the selective etching provides a net deposition of a fluo... | 03/23/2010 |
| 7645707 | Etch profile control A method for etching a dielectric layer over a substrate and disposed below a mask is provided. The substrate is placed in a plasma processing chamber. An etchant gas comprising O2 and a sulfur component gas comprising at least one of H2S and a... | 01/12/2010 |
| 7622395 | Two-step method for etching a fuse window on a semiconductor substrate A two-step method for etching a fuse window on a semiconductor substrate is provided. A semiconductor substrate having thereon a fuse interconnect-wire is formed in a dielectric film stack. The dielectric film stack includes a target dielectric layer overlying said ... | 11/24/2009 |
| 7618895 | Method for etching doughnut-type glass substrates A method for etching doughnut-type glass substrates, which comprises laminating a plurality of doughnut-type glass substrates each having a circular hole at its center so that the circular holes form a cylindrical hole, and applying an etching treatment to inner per... | 11/17/2009 |
| 7611995 | Method for removing silicon oxide film and processing apparatus A silicon dioxide film removing method is capable of removing a silicon dioxide film, such as a natural oxide film or a chemical oxide film, at a temperature considerably higher than a room temperature. The silicon dioxide film removing method of removing a silicon ... | 11/03/2009 |
| 7560391 | Forming of trenches or wells having different destinations in a semiconductor substrate A method for forming, in a semiconductor substrate, wells and/or trenches having different destinations, including the steps of at least partly simultaneously etching cavities according to the pattern of the trenches and/or wells; closing the openings of the cavitie... | 07/14/2009 |
| 7541292 | Plasma etch process with separately fed carbon-lean and carbon-rich polymerizing etch gases in independent inner and outer gas injection zones A plasma etch process for etching high aspect ratio openings in a dielectric film on a workpiece is carried out in a reactor having a ceiling electrode overlying the workpiece and an electrostatic chuck supporting the workpiece. The process includes injecting a firs... | 06/02/2009 |
| 7501349 | Sequential oxide removal using fluorine and hydrogen A method is provided for oxide removal from a substrate. The method includes providing the substrate in a process chamber where the substrate has an oxide layer formed thereon, and performing a sequential oxide removal process. The sequential oxide removal process i... | 03/10/2009 |
| 7459402 | Protection layers in micromirror array devices To protect the structural layers from being eroded in the etching process, a protection layer is deposited on the exposed structural layers of the micromirror. The protection layer is deposited before etching and removed after etching. ... | 12/02/2008 |
| 7442633 | Decoupling capacitor for high frequency noise immunity Systems and methods are provided for an on-chip decoupling device and method. One aspect of the present subject matter is a capacitor. One embodiment of the capacitor includes a substrate, a high K dielectric layer doped with nano crystals disposed on the substrate,... | 10/28/2008 |
| 7439087 | Semiconductor device and manufacturing method thereof A technology for reducing distance between adjacent pixel electrodes to smaller than the limit set by conventional process margin and also preventing adjacent pixel electrodes from being short circuited is provided. In a manufacturing method of a semiconducto... | 10/21/2008 |
| 7435644 | Method of manufacturing capacitor of semiconductor device Provided is a method of manufacturing a capacitor of a semiconductor device, which can prevent tilting or an electrical short of a lower electrode. In the method, a mesh-type bridge insulating layer is formed above the contact plug on a mold oxide layer. The mold ox... | 10/14/2008 |
| 7435354 | Treatment method for surface of photoresist layer and method for forming patterned photoresist layer A treatment method for a surface of a photoresist layer is provided. After forming a patterned photoresist layer over a wafer, a surface treatment step is performed to the photoresist layer by using at least one reaction gas comprising hydrogen bromide or hydrogen i... | 10/14/2008 |
| 7432205 | Method for controlling polishing process The invention is directed to a method for controlling a polishing process. The method comprises steps of providing a first wafer, wherein a thin film is located over the first wafer. A film average thickness distribution is obtained by measuring a plurality of thick... | 10/07/2008 |
| 7432207 | Method for etching object to be processed An object to be processed has a structure having an SiC film and an organic Si-low dielectric constant film formed on the SiC film. The SiC film is etched using a plasma produced from an etching gas and using the organic Si low-dielectric constant film as a mask. Th... | 10/07/2008 |
| 7429533 | Pitch reduction A method for providing features in an etch layer is provided. A sacrificial patterned layer with sacrificial features is provided over an etch layer. Conformal sidewalls are formed in the sacrificial features, comprising at least two cycles of a sidewall formation p... | 09/30/2008 |
| 7425277 | Method for hard mask CD trim Broadly speaking, methods and an apparatus are provided for removing an inorganic material from a substrate. More specifically, the methods provide for removing the inorganic material from the substrate through exposure to a high density plasma generated using an in... | 09/16/2008 |
| 7422020 | Aluminum incorporation in porous dielectric for improved mechanical properties of patterned dielectric A porous dielectric layer is formed on a substrate. Aluminum is incorporated in the porous dielectric layer with a pattern process using an Aluminum gas precursor. The incorporated Aluminum improves the mechanical properties of the porous dielectric layer. ... | 09/09/2008 |
| 7419908 | Process for making an array of wells A method of fabricating electronic, optical or magnetic devices requiring an array of large numbers of small feature in which regions defining individual features of the array are foamed by the steps of: (a) depositing a very thin film of a highly soluble solid onto... | 09/02/2008 |
| 7416992 | Method of patterning a low-k dielectric using a hard mask By using a non-metallic hard mask for patterning low-k dielectric materials of advanced semiconductor devices, an enhanced degree of etch fidelity is obtained. The present invention may readily be applied to via first-trench last, trench first-via last schemes. ... | 08/26/2008 |
| 7416973 | Method of increasing the etch selectivity in a contact structure of semiconductor devices By providing an additional silicon dioxide based etch stop layer, a corresponding etch process for forming contact openings for directly connecting polysilicon lines and active areas may be controlled in a highly reliable manner. In another aspect, the etch selectiv... | 08/26/2008 |
| 7410901 | Submicron device fabrication A method for fabricating substrate material to include trenches and unreleased beams with submicron dimensions includes etching a first oxide layer on the substrate to define a first set of voids in the first oxide layer to expose the substrate. A second oxide layer... | 08/12/2008 |
| 7407597 | Line end shortening reduction during etch A method for etching features in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with at least one photoresist line having a pair of sidewalls ending at a line end. A coating is placed over the photoresist line comprising at lea... | 08/05/2008 |
| 7402529 | Method of applying cladding material on conductive lines of MRAM devices A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive mater... | 07/22/2008 |
| 7396770 | Post-parting etch to smooth silicon sliders To smooth silicon sliders that have been parted from each other on a wafer by DRIE, an isotropic etch using fluorine either in a gas or in an aqueous solution is performed prior to separating the individual sliders from the wafer. ... | 07/08/2008 |
| 7396772 | Method for fabricating semiconductor device having capacitor A method for fabricating a semiconductor device includes: providing a substrate structure including a bit line and a capacitor formed apart from each other at a different level; forming first, second, and third insulation layers over the bit line, the second insulat... | 07/08/2008 |
| 7393793 | Tunable-wavelength optical filter and method of manufacturing the same A method of manufacturing a tunable wavelength optical filter. The method includes steps of forming a first sacrificial oxide film for floating a lower mirror on a semiconductor substrate; sequentially laminating conductive silicon films and oxide films for defining... | 07/01/2008 |
| 7393778 | Semiconductor device and method for fabricating the same A semiconductor device and a method for fabricating the same in which a protective oxide layer is formed on an insulating interlayer gap are disclosed. An example semiconductor device includes a semiconductor substrate having lower structures, an insulating interlay... | 07/01/2008 |
