"There is practically no chance communications space satellites will be used to provide better telephone, telegraph, television, or radio service inside the United States."
T. Craven, FCC Commissioner ; 1961
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8105953 | Method of manufacturing a semiconductor device A semiconductor manufacturing apparatus includes a chamber, a gas supplier, a vacuum pump, an electrode, a conductive knitted wire mesh and a radio frequency power supply. The electrode is placed outside of the chamber and fixed to the chamber. The gas supplier supp... | 01/31/2012 |
| 7776752 | Method of etching for multi-layered structure of semiconductors in group III-V and method for manufacturing vertical cavity surface emitting laser device Provided are an etching method for a multi-layered structure of semiconductors in groups III-V and a method of manufacturing a VCSEL using the etching method. According to the etching method, a stacked structure including a first semiconductor layer and a second sem... | 08/17/2010 |
| 7737043 | Inspection method of compound semiconductor substrate, compound semiconductor substrate, surface treatment method of compound semiconductor substrate, and method of producing compound semiconductor crystal There are provided an inspection method of a compound semiconductor substrate that can have the amount of impurities at the surface of the compound semiconductor substrate reduced, a compound semiconductor substrate, a surface treatment method of a compound semicond... | 06/15/2010 |
| 7666795 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device includes forming a SiGe layer on a Si substrate, forming a dummy pattern to expose a surface of the Si substrate, and wet etching the SiGe layer while an etchant is contacted with, the dummy pattern. ... | 02/23/2010 |
| 7436075 | Ion beam irradiation apparatus and ion beam irradiation method The ion beam irradiation apparatus has a vacuum chamber 10, an ion source 2, a substrate driving mechanism 30, rotation shafts 14, arms 12, and a motor. The ion source 2 is disposed inside the vacuum chamber 10, and e... | 10/14/2008 |
| 7429534 | Etching a nitride-based heterostructure An improved solution for producing nitride-based heterostructure(s), heterostructure device(s), integrated circuit(s) and/or Micro-Electro-Mechanical System(s) is provided. A nitride-based etch stop layer that includes Indium (In) is included in a heterostructure. A... | 09/30/2008 |
| 7413958 | GaN-based permeable base transistor and method of fabrication An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same. ... | 08/19/2008 |
| 7390750 | Method of patterning elements within a semiconductor topography A method is provided which includes forming a hardmask feature adjacent to a patterned sacrificial structure of a semiconductor topography, selectively removing the patterned sacrificial structure to expose a lower layer and etching exposed portions of the lower lay... | 06/24/2008 |
| 7387967 | Columnar structured material and method of manufacturing the same A method of manufacturing a dot pattern includes the steps of preparing a structured material composed of a plurality of columnar members containing a first component and a region containing a second component different from the first component surrounding the colum... | 06/17/2008 |
| 7375037 | Fabrication method for semiconductor integrated circuit device To improve the shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. The... | 05/20/2008 |
| 7368394 | Etch methods to form anisotropic features for high aspect ratio applications Methods for forming anisotropic features for high aspect ratio application in etch process are provided in the present invention. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios through a side... | 05/06/2008 |
| 7364832 | Wet developable hard mask in conjunction with thin photoresist for micro photolithography A novel process for using a hard mask or protective layer in conjunction with an extremely thin photoresist is provided. In this process, a thin film of the protective layer is coated on the surface of a substrate that is to be selectively modified by reactive ion e... | 04/29/2008 |
| 7349612 | Optical element, optical circuit provided with the optical element, and method for producing the optical element An optical element of the present invention includes a structure having at least one convex portion and at least one concave portion formed so as to be adjacent to either one of the convex portions. At least one surface of the structure is covered, and the optical e... | 03/25/2008 |
| 7341952 | Multi-layer hard mask structure for etching deep trench in substrate A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first ... | 03/11/2008 |
| 7338826 | Silicon nitride passivation with ammonia plasma pretreatment for improving reliability of AlGaN/GaN HEMTs This invention pertains to an electronic device and to a method for making it. The device is a heterojunction transistor, particularly a high electron mobility transistor, characterized by presence of a 2 DEG channel. Transistors of this invention contain an AlGaN b... | 03/04/2008 |
| 7338821 | Method for the passivation of the mirror-faces surfaces of optical semi-conductor elements The aim of the invention is to simplify known passivation methods. According to said method, the semi-conductor elements are heated and cleaned in a high vacuum with a gaseous, reactive low-energy medium. A closed, insulating or slightly conductive, transparent prot... | 03/04/2008 |
| RE40028 | Liquid crystal display device and method of manufacturing the same The present invention discloses a method of manufacturing a liquid crystal display device including a first photolithography process forming a gate electrode on a substrate; a second photolithography process including: a) depositing sequentially a gate insulating la... | 01/22/2008 |
| 7316979 | Method and apparatus for providing an integrated active region on silicon-on-insulator devices A method and apparatus for providing integrated active regions on silicon-on-insulator (SOI) devices by oxidizing a portion of the active layer. When the active layer of the SOI wafer is relatively thick, such as about 200 Å to 1000 Å or greater, the etching pro... | 01/08/2008 |
| 7309656 | Method for forming step channel of semiconductor device A method for forming a step channel of a semiconductor device is disclosed. The method for forming a step channel of a semiconductor device comprises forming a hard mask layer pattern defining a step channel region on a semiconductor substrate, forming a spacer on a... | 12/18/2007 |
| 7288486 | Method for manufacturing semiconductor device having via holes In a method for manufacturing a semiconductor device wherein via holes are formed in an SiC substrate, a stacked film consisting of a Ti film and an Au film is formed on the back face of the SiC substrate, and a Pd film is formed thereon. Then, an Ni film is formed ... | 10/30/2007 |
| 7282454 | Switched uniformity control A component delivery mechanism for distributing a component inside a process chamber is disclosed. The component is used to process a work piece within the process chamber. The component delivery mechanism includes a plurality of component outputs for outputting the... | 10/16/2007 |
| 7268085 | Method for fabricating semiconductor device The present invention relates to a method for forming a storage node contact of a semiconductor device. The method includes the steps of: depositing sequentially a conductive layer, a nitride layer and a polysilicon layer on a substrate having an insulating structur... | 09/11/2007 |
| 7262137 | Dry etching process for compound semiconductors Accordingly, this invention relates to an dry etching process for semiconductor wafers. More particularly, the present invention discloses a dry etching process including a halogen etchant (24) and a nitrogen gas (28) that selectively etches a compound... | 08/28/2007 |
| 7259102 | Etching technique to planarize a multi-layer structure The present invention is directed to a method of etching a multi-layer structure formed from a layer of a first material and a layer of a second material differing from the first material to obtain a desired degree of planarization. To that end, the method includes ... | 08/21/2007 |
| 7256134 | Selective etching of carbon-doped low-k dielectrics The present invention includes a process for selectively etching a low-k dielectric material formed on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a fluorine-rich fluorocarbon or hydrofluorocarbon gas, a nitrogen-c... | 08/14/2007 |
| 7250349 | Method for forming ferroelectric memory capacitor A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched t... | 07/31/2007 |
| 7247252 | Method of avoiding plasma arcing during RIE etching A method for avoiding plasma arcing during a reactive ion etching (RIE) process including providing a semiconductor wafer having a process surface for depositing a dielectric insulating layer; depositing at least a portion of a dielectric insulating layer to form a ... | 07/24/2007 |
| 7241694 | Method for manufacturing semiconductor device having trench in silicon carbide semiconductor substrate A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a tre... | 07/10/2007 |
| 7208423 | Semiconductor device fabrication method and semiconductor device A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask... | 04/24/2007 |
| 7196017 | Method for etching smooth sidewalls in III-V based compounds for electro-optical devices III-V based compounds are etched to produce smooth sidewalls for electro-optical applications using BCl3 together with chemistries of CH4 and H2 in RIE and/or ICP systems. HI or IBr or some combination of group VII gaseous species (B... | 03/27/2007 |
| 7176139 | Etching method in a semiconductor processing and etching system for performing the same Disclosed is an etching method for semiconductor processing by which a pattern loading phenomenon is reduced. First, plasma is generated while setting a bias power applied to a wafer to zero and applying a source power. After a predetermined time period, an etching ... | 02/13/2007 |
| 7169709 | Laser etching method and apparatus therefor The invention provides a laser etching method for optical ablation working by irradiating a work article formed of an inorganic material with a laser light from a laser oscillator capable of emitting in succession light pulses of a large energy density in space and ... | 01/30/2007 |
| 7160789 | Shallow trench isolation and method of forming the same A shallow trench isolation (STI) structure and a method of forming the STI structure. The STI structure defines an active region formed with a recess channel transistor. The STI structure includes a STI trench has a laterally curved rounding portion on the bottom of... | 01/09/2007 |
| 7157299 | Nanofabrication of InAs/A1Sb heterostructures A heterostructure comprising: a buffer layer; a bottom barrier layer formed on the buffer layer; a quantum well layer formed on the bottom barrier layer; a top barrier layer formed on the quantum well layer; and a p-doped cap layer formed on the top barrier layer; w... | 01/02/2007 |
| 7157379 | Strained semiconductor structures A method for in situ formation of low defect, strained silicon and a device formed according to the method are disclosed. In one embodiment, a silicon germanium layer is formed on a substrate, and a portion of the silicon germanium layer is removed to expose a surfa... | 01/02/2007 |
| 7148149 | Method for fabricating nitride-based compound semiconductor element A method for fabricating a nitride semiconductor element according to the present invention comprises the steps of: forming a nitride semiconductor layer 13 on a base substrate 11; forming, on part of the upper surface of the nitride semiconductor laye... | 12/12/2006 |
| 7147709 | Non-contact etch annealing of strained layers The present invention provides a method of forming a strained semiconductor layer. The method comprises growing a strained first semiconductor layer, having a graded dopant profile, on a wafer, having a first lattice constant. The dopant imparts a second lattice con... | 12/12/2006 |
| 7135411 | Method for etching mesa isolation in antimony-based compound semiconductor structures Antimony-based semiconductor devices are formed over a substrate structure (10) that includes an antimony-based buffer layer (24) and an antimony-based buffer cap (26). Multiple epitaxial layers (30–42) formed over the substrate structu... | 11/14/2006 |
| 7125741 | Rework process of patterned photo-resist layer A rework process of patterned photo-resist layer is provided. First, a substrate is provided with a first DARC, a first primer and a first patterned photo-resist layer being sequentially formed thereon. Next, remove the first patterned photo-resist layer and the fir... | 10/24/2006 |
| 7101805 | Envelope follower end point detection in time division multiplexed processes The present invention provides a method and an apparatus for establishing endpoint during an alternating cyclical etch process or time division multiplexed process. A substrate is placed within a plasma chamber and subjected to an alternating cyclical process having... | 09/05/2006 |