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| Number | Title | Issue Date |
| 8173550 | Method for positioning spacers for pitch multiplication Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etc... | 05/08/2012 |
| 8133818 | Method of forming a hard mask pattern in a semiconductor device In a method of forming a hard mask pattern in a semiconductor device, only processes for forming patterns having a row directional line shape and a column directional line shape on a plane are performed so that the hard mask patterns can be formed to define densely ... | 03/13/2012 |
| 8124540 | Hardmask trim method A method for forming features in a polysilicon layer is provided. A hardmask layer is formed over the polysilicon layer. A photoresist mask is formed over the hardmask layer. The hardmask layer is etched through the photoresist mask to form a patterned hardmask. The... | 02/28/2012 |
| 8071485 | Method of semiconductor manufacturing for small features Small feature patterning is accomplished using a multilayer hard mask (HM). Embodiments include sequentially forming a first HM layer and a multilayer HM layer over a substrate, the multilayer HM layer comprising sublayers, etching the multilayer HM layer to form a ... | 12/06/2011 |
| 8071484 | Method of forming fine pattern employing self-aligned double patterning There are provided a method of forming a fine pattern employing self-aligned double patterning. The method includes providing a substrate. First mask patterns are formed on the substrate. A reactive layer is formed on the substrate having the first mask patterns. Th... | 12/06/2011 |
| 8067314 | Gate trim process using either wet etch or dry etch approach to target CD for selected transistors Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding ... | 11/29/2011 |
| 8062981 | Method of forming pattern using fine pitch hard mask A method of forming a fine pattern of a semiconductor device using a fine pitch hard mask is provided. A first hard mask pattern including first line patterns formed on an etch target layer of a substrate with a first pitch is formed. A first layer including a top s... | 11/22/2011 |
| 8048811 | Method for patterning a metallization layer by reducing resist strip induced damage of the dielectric material By forming a hardmask layer in combination with one or more cap layers, undue exposure of a sensitive dielectric material to resist stripping etch ambients may be reduced and integrity of the hardmask may also be maintained so that the trench etch process may be per... | 11/01/2011 |
| 8048812 | Pitch reduced patterns relative to photolithography features Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern. Pitch multiplicat... | 11/01/2011 |
| 8021985 | Method to form semiconductor laser diode The process of the present invention to form a mask made of inorganic material containing silicon reduces the plasma damage induced in the semiconductor layers due to the plasma-ashing. The semiconductor material is heat-treated at a high temperature after the growt... | 09/20/2011 |
| 8008210 | Exposure mask with double patterning technology and method for fabricating semiconductor device using the same An exposure mask for forming a G-type active region with a double patterning technology includes a bar shaped first light-blocking pattern to define an I-type active region, and an island shaped second light-blocking pattern to define a bit line contact region. The ... | 08/30/2011 |
| 8008211 | Pattern forming method, semiconductor device manufacturing apparatus and storage medium A pattern forming method includes (a) forming pairs of deposits on sidewalls of mask portions in first mask patterns by forming a thin film thereon, etching it to leave deposits, and exposing a top surface of a second-layer film between the deposits; (b) forming sec... | 08/30/2011 |
| 8003542 | Multiple spacer steps for pitch multiplication Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etc... | 08/23/2011 |
| 8003544 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device according to an embodiment includes processing a second film 14 formed on a semiconductor substrate to a pattern including a plurality of linear parts and end portions formed in an end of each of the linear par... | 08/23/2011 |
| 8003543 | Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced fr... | 08/23/2011 |
| 7998872 | Method for etching a silicon-containing ARC layer to reduce roughness and CD A method of dry developing a multi-layer mask having a silicon-containing anti-reflective coating (ARC) layer on a substrate is described. The method comprises forming the multi-layer mask on the substrate, wherein the multi-layer mask comprises a lithographic layer... | 08/16/2011 |
| 7985692 | Method to reduce charge buildup during high aspect ratio contact etch A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopant... | 07/26/2011 |
| 7977248 | Double patterning with single hard mask In general, in one aspect, a method includes forming a hard mask on a semiconductor substrate. A first resist layer is patterned on the hard mask as a first plurality of lines separated by a first defined pitch. The hard mask is etched to a portion of formed thickne... | 07/12/2011 |
| 7955987 | Exposure mask and method of forming a contact hole of a semiconductor device employing the same An exposure mask and a method of forming a contact hole of a semiconductor device using the same, in which micro patterns can be formed are disclosed herein. In an aspect, an exposure mask method includes a mask substrate, a light-shield pattern formed on the mask s... | 06/07/2011 |
| 7939451 | Method for fabricating a pattern A method for fabricating a patter is provided as followed. First, a material layer is provided, whereon a patterned hard mask layer is formed. A spacer is deposited on the sidewalls of the patterned hard mask layer. Then, the patterned hard mask layer is removed, an... | 05/10/2011 |
| 7932183 | Method of manufacturing multilayer thin film pattern and display device A method of manufacturing a multilayer thin film pattern includes forming a metal film over a substrate, forming a second thin film over the metal film, forming a resist pattern over the second thin film, etching the second thin film using the resist pattern as a ma... | 04/26/2011 |
| 7910489 | Infinitely selective photoresist mask etch A method for etching features into an etch layer disposed below a photoresist mask without an intermediate hardmask is provided. A plurality of etch cycles are provided. Each etch cycle comprises providing a deposition etch phase that etches features into the etch l... | 03/22/2011 |
| 7906435 | Semiconductor device and a manufacturing method thereof A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in serie... | 03/15/2011 |
| 7902079 | Method for fabricating recess pattern in semiconductor device A method for fabricating a recess pattern in a semiconductor device includes defining an active region on a substrate, forming a first mask pattern over the active region in a line type structure, forming a second mask pattern comprising an open region over the acti... | 03/08/2011 |
| 7892982 | Method for forming fine patterns of a semiconductor device using a double patterning process A method for forming fine patterns of a semiconductor device includes forming an etching film on a substrate having first and second areas, forming first mask patterns on the substrate to have a first pattern density in the first area and a second pattern density in... | 02/22/2011 |
| 7892981 | Method of forming a micro pattern of a semiconductor device A method of forming a micro pattern of a semiconductor device includes forming an etch target layer, a hard mask layer, a Bottom Anti-Reflective Coating (BARC) layer and a first photoresist pattern over a semiconductor substrate. An organic layer is formed on a surf... | 02/22/2011 |
| 7888269 | Triple layer anti-reflective hard mask A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si3N4) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over t... | 02/15/2011 |
| 7867912 | Methods of manufacturing semiconductor structures A method of manufacturing semiconductor structures is disclosed. In one embodiment, a first mask is provided above a substrate. The first mask includes first mask lines extending along a first axis. A second mask is provided above the first mask. The second mask inc... | 01/11/2011 |
| 7851369 | Hardmask trim method A method for forming features in a polysilicon layer is provided. A hardmask layer is formed over the polysilicon layer. A photoresist mask is formed over the hardmask layer. The hardmask layer is etched through the photoresist mask to form a patterned hardmask. The... | 12/14/2010 |
| 7838433 | Cluster tool and method for process integration in manufacturing of a photomask A method and apparatus for process integration in manufacture of a photomask are disclosed. In one embodiment, a cluster tool suitable for process integration in manufacture of a photomask including a vacuum transfer chamber having coupled thereto at least one hard ... | 11/23/2010 |
| 7833911 | Method of manufacturing semiconductor device, apparatus of manufacturing semiconductor device and semiconductor device A method of manufacturing a semiconductor device includes: etching a first film provided on a wafer in a chamber; removing at least part of reaction products deposited on a component in the chamber facing the wafer by the etching to cause a distribution state of the... | 11/16/2010 |
| 7829471 | Cluster tool and method for process integration in manufacturing of a photomask A method and apparatus for process integration in manufacture of a photomask are disclosed. In one embodiment, a cluster tool suitable for process integration in manufacture of a photomask including a vacuum transfer chamber having coupled thereto at least one hard ... | 11/09/2010 |
| 7811940 | Topography directed patterning A pattern having exceptionally small features is formed on a partially fabricated integrated circuit during integrated circuit fabrication. The pattern comprises features formed by self-organizing material, such as diblock copolymers. The organization of the copolym... | 10/12/2010 |
| 7807583 | High aspect ratio via etch A method for patterning high aspect ratio vias is provided. More specifically a dry etching method is provided for patterning deep vias or vias with high aspects ratios thereby eliminating the hard mask undercut. A method is provided to create (pattern) deep vias in... | 10/05/2010 |
| 7807582 | Method of forming contacts for a memory device The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer abov... | 10/05/2010 |
| 7799695 | Device for liquid treatment of wafer-shaped articles A device for liquid treatment of a defined area of a wafer-shaped article, especially of a wafer, in which a mask is kept at a defined short distance to the wafer-shaped article such that liquid can be retained between the mask and the defined area of the wafer-shap... | 09/21/2010 |
| 7790619 | Method for fabricating semiconductor device having narrow channel A method for fabricating a semiconductor device including forming a gate insulation layer, a conductive layer for a gate electrode, and an insulation layer for a gate hard mask over a substrate, selectively etching the insulation layer for a gate hard mask and the c... | 09/07/2010 |
| 7781347 | Semiconductor device having multiple-layer hard mask with opposite stresses and method for fabricating the same A semiconductor device includes a hard mask including a first layer and a second layer in contact with each other and having opposite stress types, wherein a difference between initial stresses of the first layer and the second layer is increased so that after a the... | 08/24/2010 |
| 7759254 | Method for forming impurity-introduced layer, method for cleaning object to be processed apparatus for introducing impurity and method for producing device A method of forming an impurity-introduced layer is disclosed. The method includes at least a step of forming a resist pattern on a principal face of a solid substrate such as a silicon substrate (S27); a step of introducing impurity into the solid substrate ... | 07/20/2010 |
| 7732340 | Method for adjusting a critical dimension in a high aspect ratio feature A method for adjusting the lateral critical dimension (i.e., length and width) of a feature formed in a layer on a substrate using a dry etching process. One or more thin intermediate sub-layers are inserted in the layer within which the feature is to be formed. Onc... | 06/08/2010 |
