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| Number | Title | Issue Date |
| 8034721 | Manufacturing method of semiconductor device A first film and a second film are formed on a semiconductor substrate in this order. A resist pattern is formed on the second film. An opening is formed by removing the second film exposed between the resist pattern at a state where the second film remains on the b... | 10/11/2011 |
| 7727898 | Semiconductor device and method of fabricating same A semiconductor device having reliable electrode contacts. First, an interlayer dielectric film is formed from a resinous material. Then, window holes are formed. The interlayer dielectric film is recessed by oxygen plasma. This gives rise to tapering window holes. ... | 06/01/2010 |
| 7696099 | Manufacturing method of semiconductor device A first film and a second film are formed on a semiconductor substrate in this order. A resist pattern is formed on the second film. An opening is formed by removing the second film exposed between the resist pattern at a state where the second film remains on the b... | 04/13/2010 |
| 7682981 | Topography transfer method with aspect ratio scaling The present invention is a method of applying a topographical surface to a part such as a substrate without the need for low temperature softening of that part while retaining high aspect ratios and densely packed features in that topography. A substrate, selected f... | 03/23/2010 |
| 7579282 | Method for removing metal foot during high-k dielectric/metal gate etching A metal layer etch process deposits, patterns and anisotropically etches a polysilicon layer (24) down to an underlying metal layer (22) to form an etched polysilicon structure (54) with polymer layers (50, 52) formed on its sidewall surf... | 08/25/2009 |
| 7538039 | Method for manufacturing a wiring over a substrate A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression betwee... | 05/26/2009 |
| 7524770 | Methods of forming image sensor microlens structures In one aspect, an image sensor is provided which includes an interlayer insulation film formed over a substrate including a light receiving device, a color filter formed over the interlayer insulation film, a protection film having a flat top face formed over the in... | 04/28/2009 |
| 7470629 | Structure and method to fabricate finfet devices There is provided a method for fabricating a FinFET in which a self-limiting reaction is employed to produce a unique and useful structure that may be detectable with simple failure analysis techniques. The structure is an improved vertical fin with a gently sloping... | 12/30/2008 |
| 7419613 | Method and device for plasma-etching organic material film A support electrode (2) and a counter electrode (16) constituting parallel plate electrodes are disposed in a process vessel (1). A substrate (W) with an organic material film formed thereon is supported by the support electrode (2). A hi... | 09/02/2008 |
| 7413915 | Micro-fluid ejection head containing reentrant fluid feed slots Methods of micro-machining a semiconductor substrate to form through fluid feed slots therein. One method includes providing a semiconductor substrate wafer having a thickness greater than about 500 microns and having a device side and a back side opposite the devic... | 08/19/2008 |
| 7410897 | Contact plug processing and a contact plug A semiconductor device has anisotropically formed via holes through a PMD layer. The anisotropic geometry of the via holes results in the diameter of a via hole over a gate structure being equal to the diameter of a via hole not over the gate structure. The via hole... | 08/12/2008 |
| 7396765 | Method of fabricating a liquid crystal display device A method of fabricating a liquid crystal display device according to an embodiment of the present invention includes forming first and second conductive layers on a substrate, wherein the first layer is transparent; patterning the second conductive layer and the fir... | 07/08/2008 |
| 7393791 | Etching method, method of fabricating metal film structure, and etching structure There is provided an etching method in which a protective film existing in an etching-destined region of a substrate structure is removed by means of ICP-RIE to form an exposure region of the principal surface of the substrate. The substrate structure comprises a su... | 07/01/2008 |
| 7390755 | Methods for post etch cleans The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise ... | 06/24/2008 |
| 7378703 | Semiconductor device having step gates and method for fabricating the same The semiconductor device includes a substrate including a first active region and a second active region having a greater height than that of the first active region. A gate pattern has a step structure, which is formed on a border region between the first active re... | 05/27/2008 |
| 7371655 | Method of fabricating low-power CMOS device A low-power CMOS device can be fabricated by forming a shallow trench on a silicon substrate using a gate mask and negative photoresist. This enables an extremely low profile for a junction after completion of lightly doped drain and source/drain implantations. The ... | 05/13/2008 |
| 7365015 | Damascene replacement metal gate process with controlled gate profile and length using SiGeas sacrificial material A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the p... | 04/29/2008 |
| 7358170 | Methods of forming conductive interconnects, and methods of depositing nickel The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which contains triethanolamine, maleic anhydride and at least one nickel sa... | 04/15/2008 |
| 7354856 | Method for forming dual damascene structures with tapered via portions and improved performance The manufacture of damascene structures having improved performance, particularly, but not by way of limitation, dual damascene structures is provided. In one embodiment, a substrate having a conductive layer is formed in a first insulating layer. A protective layer... | 04/08/2008 |
| 7341922 | Dry etching method, fabrication method for semiconductor device, and dry etching apparatus When etching is performed with respect to a silicon-containing material by using a dry etching apparatus having a dual power source, the application of bias power is initiated before oxidization proceeds at a surface of the silicon-containing material. Specifically,... | 03/11/2008 |
| 7338906 | Method for fabricating semiconductor device The present invention relates to a method for fabricating a semiconductor device with a fine pattern even without decreasing a line width of a photoresist pattern. The method includes the steps of: forming a target etching layer on a substrate; forming a plurality o... | 03/04/2008 |
| 7335593 | Method of fabricating semiconductor device A gate metal is formed in a film, the foregoing gate metal is partially etched per each TFT having a different property, and a gate electrode is fabricated. Specifically, a resist mask is fabricated by exposing a resist to light per each TFT having a different prope... | 02/26/2008 |
| 7323743 | Floating gate A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A ... | 01/29/2008 |
| 7320927 | In situ hardmask pullback using an in situ plasma resist trim process The present invention provides a process of manufacturing an isolation structure for use in a semiconductor device. The process includes forming an opening in a substrate through a patterned photoresist layer 225 and a hardmask layer 215 located over t... | 01/22/2008 |
| 7320897 | Electroluminescence device with nanotip diodes A nanotip electroluminescence (EL) diode and a method are provided for fabricating said device. The method comprises: forming a plurality of Si nanotip diodes; forming a phosphor layer overlying the nanotip diode; and, forming a top electrode overlying the phosphor ... | 01/22/2008 |
| 7307025 | Lag control A method for etching features in a silicon oxide based dielectric layer over a substrate, comprising performing an etch cycle. A lag etch partially etching features in the silicon oxide based dielectric layer is performed, comprising providing a lag etchant gas, for... | 12/11/2007 |
| 7303945 | Method for forming pattern of stacked film and thin film transistor A method for forming a pattern of a stacked film, includes steps (a) to (e). The step (a) is forming sequentially a first base insulating film and a light shielding material on a transparent substrate. The step (b) is patterning the light shielding material to obtai... | 12/04/2007 |
| 7291360 | Chemical vapor deposition plasma process using plural ion shower grids A chemical vapor deposition process is carried out in a reactor chamber having a set of plural parallel ion shower grids that divide the chamber into an upper ion generation region and a lower process region, each of the ion shower grids having plural orifices in mu... | 11/06/2007 |
| 7291439 | Photoresist composition, method for forming film pattern using the same, and method for manufacturing thin film transistor array panel using the same A photoresist composition, a method for forming a film pattern using the photoresist composition, and a method for manufacturing a thin film transistor array panel using the photoresist composition are provided. In one embodiment, a photoresist composition includes ... | 11/06/2007 |
| 7282802 | Modified via bottom structure for reliability enhancement The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures de... | 10/16/2007 |
| 7265025 | Method for filling trench and relief geometries in semiconductor structures A method teaches how to fill trench structures formed in a semiconductor substrate. The trench structures are coated in a first deposition process with a first primary filling layer with a high conformity and minimal roughness. A V etching reaching down to a predete... | 09/04/2007 |
| 7262433 | Semiconductor device A first thin film transistor including a gate electrode, a source region, a drain region, a GOLD region, and a channel region is formed at a first region at a TFT array substrate. A second thin film transistor including a gate electrode, a source region, drain regio... | 08/28/2007 |
| 7259089 | Semiconductor device manufacturing method that includes forming a wiring pattern with a mask layer that has a tapered shape A semiconductor device manufacturing method includes the steps of: forming first and second insulation films on a substrate provided with a first wiring; sequentially forming first to third mask layers on the second insulation film; forming a wiring groove pattern i... | 08/21/2007 |
| 7256134 | Selective etching of carbon-doped low-k dielectrics The present invention includes a process for selectively etching a low-k dielectric material formed on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a fluorine-rich fluorocarbon or hydrofluorocarbon gas, a nitrogen-c... | 08/14/2007 |
| 7256121 | Contact resistance reduction by new barrier stack process The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top port... | 08/14/2007 |
| 7247573 | Process for forming tapered trenches in a dielectric material A process for forming a tapered trench in a dielectric material includes the steps of forming a dielectric layer on a semiconductor wafer, and plasma etching the dielectric layer; during the plasma etch, the dielectric layer is chemically and physically etched simul... | 07/24/2007 |
| 7244474 | Chemical vapor deposition plasma process using an ion shower grid A chemical vapor deposition process is carried out in a reactor chamber with an ion shower grid that divides the chamber into an upper ion generation region and a lower process region, the ion shower grid having plural orifices oriented in a non-parallel direction r... | 07/17/2007 |
| 7241693 | Processing method for protection of backside of a wafer A temporal protection layer is employed to a wafer backside for use of micro-electro-mechanical systems (MEMS). The formation of the temporal protection layer prevents the wafer backside from scratch in process of transferring system for IC manufacturers. With regar... | 07/10/2007 |
| 7238609 | Method for fabricating semiconductor device A method for fabricating a semiconductor device has the steps of forming a conductive film on a substrate, forming an insulating film such that the conductive film is covered with the insulating film, forming, in the insulating film, a hole having a bottom portion n... | 07/03/2007 |
| 7227218 | Method and system for forming source regions in memory devices A memory device and the method for manufacturing same is disclosed. The device comprises a first oxide layer on top of a substrate, a floating gate layer on top of the first oxide layer, a second oxide layer over the floating gate layer, wherein the second oxide lay... | 06/05/2007 |
