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| Number | Title | Issue Date |
| 7981804 | Manufacturing method of semiconductor device A method of forming a metal interconnection that has a favorable cross-sectional shape is provided without the fear of side etching, even in a sparse arrangement of metal interconnections. The method, the following structure is employed. A region for placing a dummy... | 07/19/2011 |
| 7935638 | Methods and structures for enhancing perimeter-to-surface area homogeneity Methods and structures for enhancing the homogeneity in a ratio of perimeter to surface area among heterogeneous features in different substrate regions. At least one shape on the substrate includes an added edge effective to reduce a difference in the perimeter-to-... | 05/03/2011 |
| 7803714 | Semiconductor through silicon vias of variable size and method of formation A through-silicon via structure is formed by providing a substrate having a first conductive catch pad and a second conductive catch pad formed thereon. The substrate is secured to a wafer carrier. A first etch of a first type is performed on the substrate underlyin... | 09/28/2010 |
| 7786017 | Utilizing inverse reactive ion etching lag in double patterning contact formation Solutions for solutions for utilizing Inverse Reactive Ion Etching lag in double patterning contact formation are disclosed. In one embodiment, a method includes providing a CMOS device including: an NMOS device having an NMOS gate and a PMOS device having a PMOS ga... | 08/31/2010 |
| 7718537 | Method for manufacturing a CBRAM semiconductor memory A method for manufacturing CBRAM switching elements and CBRAM semiconductor memories with improved switching characteristics so as to remove superfluous, weak, cluster-like, or unbound selenium at the surface of a GeSe layer is solved by the present invention in tha... | 05/18/2010 |
| 7557044 | Nanomachined mechanical components using nanoplates, methods of fabricating the same and methods of manufacturing nanomachines Disclosed herein is a method of fabricating nano-components using nanoplates, including the steps of: printing a grid on a substrate using photolithography and Electron Beam Lithography; spraying an aqueous solution dispersed with nanoplates onto the grid portion to... | 07/07/2009 |
| 7498268 | Gas delivery system for semiconductor processing The present invention is directed to improving defect performance in semiconductor processing systems. In specific embodiments, an apparatus for processing semiconductor substrates comprises a chamber defining a processing region therein, and a substrate support dis... | 03/03/2009 |
| 7482278 | Key-hole free process for high aspect ratio gap filling with reentrant spacer A new method of depositing PE-oxide or PE-TEOS. An HDP-oxide is provided over a pattern of polysilicon. An etch back is performed to the deposited HDP-oxide, a layer of plasma-enhanced SiN is deposited. This PE-SiN is etched back leaving SiN spacers on the sidewalls... | 01/27/2009 |
| 7446050 | Etching and plasma treatment process to improve a gate profile A method for improving a polysilicon gate electrode profile to avoid preferential RIE etching in a polysilicon gate electrode etching process including carrying out a multi-step etching process wherein at least one of a lower RF source power and RF bias power are re... | 11/04/2008 |
| 7442650 | Methods of manufacturing semiconductor structures using RIE process A method for etching on a semiconductors at the back end of line using reactive ion etching. The method comprises reduced pressure atmosphere and a mixture of gases at a specific flow rate ratio during plasma generation and etching. Plasma generation is induced by a... | 10/28/2008 |
| 7442624 | Deep alignment marks on edge chips for subsequent alignment of opaque layers A method of forming alignment marks on edge chips in a kerf region of a semiconductor workpiece. The alignment marks are formed in at least one material layer of the semiconductor device. The alignment marks are formed using a separate lithography mask, and may exte... | 10/28/2008 |
| 7439093 | Method of making a MEMS device containing a cavity with isotropic etch followed by anisotropic etch A method of making an etch structure in a substrate involves the steps of providing a mask on a substrate with a pattern that leaves at least one opening leaving the substrate in direct contact with the ambient, performing an isotropic or quasi-isotropic etch throug... | 10/21/2008 |
| 7439183 | Method of manufacturing a semiconductor device, and a semiconductor substrate A method of manufacturing a semiconductor device. In the method, a thin film is formed on an Si substrate having face orientation (100), that part of the thin film, which lies on an element-isolating region, is removed. Then, the Si substrate is subjected to ... | 10/21/2008 |
| 7427566 | Method of making an electronic device cooling system A method is provided. The method includes forming a conductive layer on an inner surface of a substrate and providing a sacrificial layer over the conductive layer. The method includes forming a plurality of channels in the sacrificial layer and plating the sacrific... | 09/23/2008 |
| 7425465 | Method of fabricating a multi-post structures on a substrate Micromechanical devices having complex multilayer structures and techniques for forming the devices are described. ... | 09/16/2008 |
| 7413915 | Micro-fluid ejection head containing reentrant fluid feed slots Methods of micro-machining a semiconductor substrate to form through fluid feed slots therein. One method includes providing a semiconductor substrate wafer having a thickness greater than about 500 microns and having a device side and a back side opposite the devic... | 08/19/2008 |
| 7410901 | Submicron device fabrication A method for fabricating substrate material to include trenches and unreleased beams with submicron dimensions includes etching a first oxide layer on the substrate to define a first set of voids in the first oxide layer to expose the substrate. A second oxide layer... | 08/12/2008 |
| 7405159 | Method of fabricating a semiconductor device package having a semiconductor element with a roughened surface A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed ... | 07/29/2008 |
| 7405152 | Reducing wire erosion during damascene processing A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of unwanted material and thus, reduces unwanted erosion of certain nearby str... | 07/29/2008 |
| 7381343 | Hard mask structure for patterning of materials Techniques for magnetic device fabrication are provided. In one aspect, a method of patterning at least one, e.g., nonvolatile, material comprises the following steps. A hard mask structure is formed on at least one surface of the material to be patterned. The hard ... | 06/03/2008 |
| 7375038 | Method for plasma etching a chromium layer through a carbon hard mask suitable for photomask fabrication Methods for etching chromium and forming a photomask using a carbon hard mask are provided. In one embodiment, a method of a chromium layer includes providing a substrate in a processing chamber, the substrate having a chromium layer partially exposed through a patt... | 05/20/2008 |
| 7375028 | Method for manufacturing a semiconductor device A semiconductor device may be manufactured by a method that includes forming an etch stop layer on a semiconductor substrate, sequentially forming a first interlayer insulating layer, a first diffusion barrier, a second interlayer insulating layer, and a second diff... | 05/20/2008 |
| 7371690 | Dry etching method and apparatus A condition without using Ar as plasma gas is applied to processing of an organic anti-reflection-coating, which suppresses a spatter effect and decreases the cleavage of C—H and OC—O bonds in a resist. As a result, roughness of the resist after processing the a... | 05/13/2008 |
| 7368396 | Dry etching methods A process for etching semiconductor substrates using a deep reactive ion etching process to produce through holes or slots (referred to collectively as “slots”) in the substrates. The process includes applying a first layer to a first surface of substrate to pro... | 05/06/2008 |
| 7368392 | Method of fabricating a gate structure of a field effect transistor having a metal-containing gate electrode A method of etching metals and/or metal-containing compounds using a plasma comprising a bromine-containing gas. In one embodiment, the method is used during fabrication of a gate structure of a field effect transistor having a titanium nitride gate electrode, an ul... | 05/06/2008 |
| 7365019 | Atmospheric process and system for controlled and rapid removal of polymers from high aspect ratio holes A system that generates an intense hot gas stream is described to etch a polymer on a substrate used in the manufacture of semiconductor and MEMS devices with no surface damage. The etching process is particularly useful to remove a polymer from relatively high aspe... | 04/29/2008 |
| 7361607 | Method for multi-layer resist plasma etch A method for etching a multi-layer resist defined over a substrate in a plasma etch chamber is provided. The method initiates with introducing the substrate having a pattern defined on a first layer of the multi-layer resist into the etch chamber. SO2 gas... | 04/22/2008 |
| 7361571 | Method for fabricating a trench isolation with spacers A method for forming a shallow trench isolation (STI) in a semiconductor device, is presented. In one embodiment, the method includes successively forming a pad oxide and a pad nitride on a silicon substrate, successively etching the pad nitride, the pad oxide, and ... | 04/22/2008 |
| 7352064 | Multiple layer resist scheme implementing etch recipe particular to each layer Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first plan... | 04/01/2008 |
| 7351664 | Methods for minimizing mask undercuts and notches for plasma processing system A method for etching silicon layer of a substrate, which is deposited on a bottom electrode in a plasma processing chamber. The method includes performing a main etch step until at least 70 percent of silicon layer is etched. The method further includes an overetch ... | 04/01/2008 |
| 7348204 | Method of fabricating solid state imaging device including filling interelectrode spacings A method for fabricating a solid state imaging device comprising photoelectric conversion sections and charge transfer sections having single-layered charge transfer electrodes for transferring charges generated in the photoelectric conversion sections, the method i... | 03/25/2008 |
| 7347915 | Plasma in-situ treatment of chemically amplified resist A method for creating semiconductor devices by etching a layer over a wafer is provided. A photoresist layer is provided on a wafer. The photoresist layer is patterned. The wafer is placed in a process chamber. The photoresist is hardened by providing a hardening pl... | 03/25/2008 |
| 7344994 | Multiple layer etch stop and etching method A process for etching semiconductor substrates using a deep reactive ion etching process to produce through holes or slots (hereinafter “slots”) in the substrates. The process includes applying a first layer to a back side of a substrate as a first etch stop mat... | 03/18/2008 |
| 7341951 | Methods of forming semiconductor constructions The invention includes methods of forming semiconductor constructions in which a single etch is utilized to penetrate through a titanium-containing layer and partially into a silicon-containing layer beneath the titanium-containing layer. The etch can utilize CH | 03/11/2008 |
| 7335590 | Method of fabricating semiconductor device by forming diffusion barrier layer selectively and semiconductor device fabricated thereby In a method of fabricating a semiconductor device by selectively forming a diffusion barrier layer, and a semiconductor device fabricated thereby, a conductive pattern and an insulating layer, which covers the conductive pattern, are formed on a semiconductor substr... | 02/26/2008 |
| 7335583 | Isolating semiconductor device structures An array of continuous diffusion regions and continuous gate electrode structures is formed over a semiconductor substrate. Interconnecting diffusion region portions and interconnecting gate electrode portions are removed to electrically isolate transistor circuitry... | 02/26/2008 |
| 7329608 | Method of processing a substrate The invention is embodied in a plasma flow device or reactor having a housing that contains conductive electrodes with openings to allow gas to flow through or around them, where one or more of the electrodes are powered by an RF source and one or more are grounded,... | 02/12/2008 |
| 7329550 | Method for analyzing the structure of deep trench capacitors and a preparation method thereof A method for analyzing the structure of deep trench capacitors and a preparation method thereof are described. A protective layer is formed on a selected inspection area. Overlying circuit layers and an upper portion of a substrate, surrounding the selected inspecti... | 02/12/2008 |
| 7323420 | Method for manufacturing multi-thickness gate dielectric layer of semiconductor device In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting... | 01/29/2008 |
| 7320927 | In situ hardmask pullback using an in situ plasma resist trim process The present invention provides a process of manufacturing an isolation structure for use in a semiconductor device. The process includes forming an opening in a substrate through a patterned photoresist layer 225 and a hardmask layer 215 located over t... | 01/22/2008 |
