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| Number | Title | Issue Date |
| 8138094 | Method for manufacturing mask Openings are formed in first and second mask layers. Next, diameter of the opening in the second mask layer is enlarged so that the diameter of the opening in the second mask layer becomes larger by a length X than diameter of the opening in the first mask layer. Th... | 03/20/2012 |
| 8093153 | Method of etching oxide layer and nitride layer An exemplary method of patterning oxide layer and removing residual nitride includes steps of forming a first oxide layer, a nitride layer, a second oxide layer and a complex hard mask on a substrate in turn. The first oxide layer covers an insulating structure. The... | 01/10/2012 |
| 8091046 | Set of masks, method of generating mask data and method for forming a pattern A method of generating mask data, for a set of masks used to transfer a pattern for delineating a circuit pattern of a semiconductor integrated circuit, includes preparing design data having a design pattern corresponding to the pattern to be transferred on a semico... | 01/03/2012 |
| 8048810 | Method for metal gate N/P patterning A method for fabricating a integrated circuit is disclosed. An exemplary method includes providing a substrate; forming a hard mask layer over the substrate; forming a patterned photoresist layer over the hard mask layer, such that portions of the hard mask layer ar... | 11/01/2011 |
| 8026179 | Patterning method and integrated circuit structure A patterning method is provided. First, a mask layer and a plurality of first transfer patterns are sequentially formed on a target layer. Thereafter, a plurality of second patterns is formed in the gaps between the first transfer patterns. Afterwards, a plurality o... | 09/27/2011 |
| 8003540 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device includes forming an underlying layer over a semiconductor substrate; forming a hard mask layer over the underlying layer; forming first etch patterns over the hard mask layer; forming second etch patterns between the... | 08/23/2011 |
| 7985686 | Method of forming a nonvolatile memory device using semiconductor nanoparticles A floating gate for a field effect transistor (and method for forming the same and method of forming a uniform nanoparticle array), includes a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of the nanoparticles is one of te... | 07/26/2011 |
| 7972966 | Etching of tungsten selective to titanium nitride The present invention in one embodiment provides an etch method that includes providing a structure including a tungsten (W) portion and a titanium nitride (TiN) portion; applying a first etch feed gas of sulfur hexafluoride (SF6) and oxygen (O2 | 07/05/2011 |
| 7972967 | Method of forming patterns of a semiconductor device including forming spacers on sidewalls of auxiliary patterns and removing exposed auxiliary patterns A method of forming patterns of a semiconductor device comprising forming an auxiliary layer over an underlying layer comprising a cell region and a select transistor region, forming a first passivation layer over the auxiliary layer, wherein the first passivation l... | 07/05/2011 |
| 7960287 | Methods for fabricating FinFET structures having different channel lengths Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The ... | 06/14/2011 |
| 7951720 | Method of forming a contact hole for a semiconductor device Forming contact holes of a semiconductor device includes forming a reaction layer that is provided with a reaction pattern on a semiconductor substrate. Subsequently, a self-assembled monolayer is formed by injecting a polymer from a functional group that is capable... | 05/31/2011 |
| 7910487 | Reverse masking profile improvements in high aspect ratio etch A method of improving high aspect ratio etching by reverse masking to provide a more uniform mask height between the array and periphery is presented. A layer of amorphous carbon is deposited over a substrate. An inorganic hard mask is deposited on the amorphous car... | 03/22/2011 |
| 7879729 | Method of forming a micro pattern of a semiconductor device In a method of forming micro patterns of a semiconductor device, first etch mask patterns are formed over a semiconductor substrate. An auxiliary film is formed over the semiconductor substrate including a surface of the first etch mask patterns. Second etch mask pa... | 02/01/2011 |
| 7863196 | Self-aligned dielectric cap A method of forming a dielectric layer includes providing a substrate that has a copper region and a non-copper region. The substrate is etched to remove any copper oxides from the copper region. A dielectric cap is then selectively formed over the copper region of ... | 01/04/2011 |
| 7851366 | Forming a sacrificial layer in order to realise a suspended element The invention relates to a method of realization of a sacrificial layer, including the steps of: lithography of a resin deposited on a substrate in order to supply a lithographed resist pattern on a substrate zone, the zone having ... | 12/14/2010 |
| 7846843 | Method for manufacturing a semiconductor device using a spacer as an etch mask for forming a fine pattern A process for manufacturing a semiconductor device using a spacer as an etch mask for forming a fine pattern is described. The process includes forming a hard mask layer over a target layer that is desired to be etched. A sacrificial layer pattern is subsequently fo... | 12/07/2010 |
| 7846844 | Method for fabricating saddle type fin transistor A method for fabricating a saddle type fin transistor includes: preparing a substrate where a device isolation structure is already formed; forming a hard mask pattern over the substrate, the hard mask pattern including a coating layer obtained through a coating met... | 12/07/2010 |
| 7842616 | Methods for fabricating semiconductor structures Methods for fabricating semiconductor structures are provided. A first layer may be deposited onto a substrate followed by the deposition of a second layer onto the first layer. A plurality of line structures may be etched in the second layer. A third layer, deposit... | 11/30/2010 |
| 7833910 | Film substrate, fabrication method thereof, and image display substrate In a film substrate (FB) including a film base material (1) and conductor wiring (23) that is formed on the film base material (1), the conductor wiring (23) is arranged such that the conductor wiring thickness of an external connection p... | 11/16/2010 |
| 7829466 | Methods for fabricating FinFET structures having different channel lengths Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The ... | 11/09/2010 |
| 7825030 | Method of forming a spacer A sacrificial layer and wet etch are used to form a sidewall spacer so as to prevent damage to the structure on which the spacer is formed and to the underlying substrate as well. Once the structure is formed on the substrate a spacer formation layer is formed to co... | 11/02/2010 |
| 7807578 | Frequency doubling using spacer mask A method for fabricating a semiconductor mask is described. A semiconductor stack having a sacrificial mask and a spacer mask is first provided. The sacrificial mask is comprised of a series of lines and the spacer mask has spacer lines adjacent to the sidewalls of ... | 10/05/2010 |
| 7786015 | Method for fabricating self-aligned complementary pillar structures and wiring A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spac... | 08/31/2010 |
| 7781345 | Method of manufacturing imprint substrate and imprinting method In a method of manufacturing an imprint substrate, a concave pattern, which is recessed, is formed on a top surface of the mold substrate. A light blocking layer is formed on the concave pattern and the top surface of the mold substrate. After bonding an adhesive su... | 08/24/2010 |
| 7776750 | Semiconductor device and method for forming a pattern in the same with double exposure technology A method for forming a pattern in a semiconductor device includes performing a double exposure process for a multifunctional hard mask layer over a semiconductor substrate using a line/space mask to form a multifunctional hard mask layer pattern having a first conta... | 08/17/2010 |
| 7687403 | Method of manufacturing flash memory device A method of manufacturing a flash memory device includes providing a substrate having an insulating layer, a first mask layer over the insulating layer, a second mask layer over the first mask layer, a first photoresist pattern over the second mask layer, the first ... | 03/30/2010 |
| 7655569 | Method of manufacturing semiconductor device The invention prevents a wiring layer in a memory region from being exposed to prevent a change in wire resistance and degradation of reliability. A SiO2 film as an etching stopper film which transmits ultraviolet light is formed on pad electrodes and an ... | 02/02/2010 |
| 7625822 | Semiconductor device and method for manufacturing the same including two antireflective coating films A method for manufacturing a semiconductor device deposits a plurality of bottom antireflective coating films to prevent a standing wave caused by a light source of a short wavelength in forming a fine pattern. The method includes forming a pattern formation layer o... | 12/01/2009 |
| 7605087 | Methods of forming semiconductor devices using di-block polymer layers A method of forming a semiconductor device is provided. An interlayer dielectric is formed on a substrate. A di-block polymer layer that includes a plurality of first polymer blocks and a plurality of second polymer blocks is formed on the interlayer dielectric. The... | 10/20/2009 |
| 7572735 | Blanket resist to protect active side of semiconductor Yield loss in semiconductor processing is mitigated by forming a resist over an active side of a semiconductor workpiece or wafer, as well as around the edge of the wafer. The resist mitigates the creation of contaminants, such as nitride flakes, for example, that c... | 08/11/2009 |
| 7553770 | Reverse masking profile improvements in high aspect ratio etch A method of improving high aspect ratio etching by reverse masking to provide a more uniform mask height between the array and periphery is presented. A layer of amorphous carbon is deposited over a substrate. An inorganic hard mask is deposited on the amorphous car... | 06/30/2009 |
| 7432120 | Method for realizing a hosting structure of nanometric elements Method for manufacturing a hosting structure of nanometric elements comprising the steps of depositing on an upper surface of a substrate, of a first material, a block-seed having at least one side wall. Depositing on at least one portion of sad surface and on the b... | 10/07/2008 |
| 7432163 | Method of manufacturing semiconductor device that includes forming adjacent field regions with a separating region therebetween A method of manufacturing a semiconductor device comprises the steps of: preparing a semiconductor substrate, the semiconductor substrate having first and second predetermined regions; forming a first field region surrounding the first predetermined region; forming ... | 10/07/2008 |
| 7410901 | Submicron device fabrication A method for fabricating substrate material to include trenches and unreleased beams with submicron dimensions includes etching a first oxide layer on the substrate to define a first set of voids in the first oxide layer to expose the substrate. A second oxide layer... | 08/12/2008 |
| 7405147 | Device and methodology for reducing effective dielectric constant in semiconductor devices A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer throu... | 07/29/2008 |
| 7396475 | Method of forming stepped structures employing imprint lithography The present invention provides a method for forming a stepped structure on a substrate that features transferring, into the substrate, an inverse shape of the stepped structure disposed on the substrate. ... | 07/08/2008 |
| 7364953 | Manufacturing method to construct semiconductor-on-insulator with conductor layer sandwiched between buried dielectric layer and semiconductor layers A method for treating exposed metal in a semiconductor wafer (301) in wafer processing is disclosed herein. In accordance with the method, a wafer is provided which is equipped with a metal layer (307) and a substrate (303), wherein a portion of... | 04/29/2008 |
| 7363598 | Dummy fill for integrated circuits A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing proc... | 04/22/2008 |
| 7356783 | Dummy fill for integrated circuits A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing proc... | 04/08/2008 |
| 7351660 | Process for producing high performance interconnects A method for fabricating high performance vertical and horizontal electrical connections in a three dimensional semiconductor structure. A dielectric film is imprinted with a stamp pattern at high vacuum and with precise temperature and stamping pressure control. Th... | 04/01/2008 |
