Did You Know...
...that the x-ray was discovered purely by accident? When German physicist Wilhelm Konrad von Roentgen was experimenting with cathode rays in 1895, he put an activated Crookes tube in a book and went out to lunch. When he returned, he discovered that a key that had also been placed in the book showed up as an image on the developed film!
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| Number | Title | Issue Date |
| 7998868 | Self-aligned masks using multi-temperature phase-change materials A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer, patterning the second layer using the multi-temperature phase-change mat... | 08/16/2011 |
| 7955983 | Defect reduction of non-polar and semi-polar III-nitrides with sidewall lateral epitaxial overgrowth (SLEO) A method of reducing threading dislocation densities in non-polar such as a-{11-20} plane and m-{1-100} plane or semi-polar such as {10-1n} plane III-Nitrides by employing lateral epitaxial overgrowth from sidewalls of etched template material through a patterned ma... | 06/07/2011 |
| 7727895 | Substrate processing system and substrate processing method Disclosed is a substrate processing method that dissolves and deforms a photoresist film having a first pattern formed on a substrate to reshape the resist film into a second pattern During the reflow process, an atmosphere of a thinner vapor-containing gas is estab... | 06/01/2010 |
| 7696096 | Self-aligned masks using multi-temperature phase-change materials A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer, patterning the second layer using the multi-temperature phase-change mat... | 04/13/2010 |
| 7410863 | Methods of forming and using memory cell structures A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a metallic material formed within the via and on a surface of the insulator... | 08/12/2008 |
| 7357873 | Polymide thin film self-assembly process The invention presents a novel polyimide-based thin film self-assembly technology, including five process steps described as follows: (1) deposits a sacrificial layer and a low-stress microstructure layer on a silicon substrate; (2) patterns and etches the low-stres... | 04/15/2008 |
| 7348278 | Method of making nitride-based compound semiconductor crystal and substrate A method of making a nitride-based compound semiconductor crystal has the step of growing a nitride-based compound semiconductor crystal with a predetermined thickness by using a nitride-based compound semiconductor substrate as a seed crystal. The nitride-based com... | 03/25/2008 |
| 7341502 | Methods and systems for planarizing workpieces, e.g., microelectronic workpieces Planarizing workpieces, e.g., microelectronic workpieces, can employ a process indicator which is adapted to change an optical property in response to a planarizing condition. This process indicator may, for example, change color in response to reaching a particular... | 03/11/2008 |
| 7335255 | Manufacturing method of semiconductor device The present invention provides a method for removing a metal element effectively from a crystalline semiconductor film obtained with the use of the metal element, without increasing the number of processes. In the present invention, an amorphous semiconductor film i... | 02/26/2008 |
| 7326606 | Semiconductor processing methods In one aspect, the invention provides a method of forming a contact opening to a conductive line. In one preferred implementation, a contact opening is formed to a conductive line which overlies a substrate isolation area with an etch which also outwardly exposes su... | 02/05/2008 |
| 7317217 | Semiconductor scheme for reduced circuit area in a simplified process An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a ... | 01/08/2008 |
| 7265055 | CMP of copper/ruthenium substrates The invention provides a method of chemically-mechanically polishing a substrate. A substrate comprising ruthenium and copper is contacted with a chemical-mechanical polishing system comprising a polishing component, hydrogen peroxide, an organic acid, at least one ... | 09/04/2007 |
| 7264976 | Advance ridge structure for microlens gapless approach A method of manufacturing a plurality of microlenses on a substrate comprises forming a grid having raised ridges defining a plurality of openings on the substrate and forming a plurality of patterned photoresist features each disposed within one of the plurality of... | 09/04/2007 |
| 7226865 | Process for forming pattern and method for producing liquid crystal display apparatus A process for forming a pattern contains steps of: forming a first mask pattern on a film to be etched on a substrate; forming a first pattern of the film to be etched by using the first mask pattern as a mask; forming a second mask pattern having a plane shape diff... | 06/05/2007 |
| 7224038 | Semiconductor device having element isolation trench and method of fabricating the same A semiconductor device capable of preventing defective embedding of an insulator and improving the withstand voltage (dielectric strength) of an element isolation region is obtained. This semiconductor device comprises a semiconductor substrate having a main surface... | 05/29/2007 |
| 7192867 | Protection of low-k dielectric in a passivation level In one embodiment, a passivation level includes a low-k dielectric. To prevent the low-k dielectric from absorbing moisture when exposed to air, exposed portions of the low-k dielectric are covered with spacers. As can be appreciated, this facilitates integration of... | 03/20/2007 |
| 7176087 | Methods of forming electrical connections In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally s... | 02/13/2007 |
| 7176138 | Selective nitride liner formation for shallow trench isolation A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectivel... | 02/13/2007 |
| 7144817 | Etching solutions and processes for manufacturing flexible wiring boards The disclosure relates to methods and solutions for precisely and rapidly etching a polyimide resin layer. Etching solutions of the present invention include 3–65% by weight of a diol containing 3 to 6 carbon atoms or a triol containing 4 to 6 carbon atoms, 10–5... | 12/05/2006 |
| 7074690 | Selective gap-fill process Methods for selectively depositing a solid material on a substrate having gaps of dimension on the order of about 100 nm or less are disclosed. The methods involve exposing the substrate to a precursor of a solid material, such that the precursor forms liquid region... | 07/11/2006 |
| 7064069 | Substrate thinning including planarization A method and intermediate structure for improving the thinning and planarity of a wafer back side utilizing planarization material applied to the back side prior to at least one portion of the thinning operation and which is subsequently removed concurrently with th... | 06/20/2006 |
| 7060623 | Method of deforming a pattern and semiconductor device formed by utilizing deformed pattern A method of deforming a pattern comprising the steps of: forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper groove, wherein the re-flow stopper groove extends outside the selecte... | 06/13/2006 |
| 7053407 | Liquid crystal display device and method for manufacturing the same Disclosed are a liquid crystal display device and a method for manufacturing the same, in which wirings connected between pads and an integrated circuit is protected from being corroded. A pixel array is formed on a display region of a substrate. A plurality of pads... | 05/30/2006 |
| 7049223 | Paste including a mixture of powders, connection plug, burying method, and semiconductor device manufacturing method Form a trench in a major surface of a semiconductor substrate, then bury a paste in the trench. The paste contains solids having a conductive substance and a resin, and solvent for dissolving the resin. The solids content of the paste is not less than 60 vol % and a... | 05/23/2006 |
| 7022608 | Method and composition for the removal of residual materials during substrate planarization A method, composition, and computer readable medium for planarizing a substrate. In one aspect, the composition includes one or more chelating agents and ions of at least one transition metal, one or more surfactants, one or more oxidizers, one or more corrosion inh... | 04/04/2006 |
| 7022579 | Method for filling via with metal A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a metallic material formed within the via and on a surface of the insulator... | 04/04/2006 |
| 7011566 | Methods and systems for conditioning planarizing pads used in planarizing substrates Monitoring the process of planarizing a workpiece, e.g., conditioning a CMP pad, can present some difficulties. Aspects of this invention provide methods and systems for monitoring and/or controlling such a planarization cycle. For example, a control system may moni... | 03/14/2006 |
| 6998348 | Method for manufacturing electronic circuits integrated on a semiconductor substrate A method for manufacturing semiconductor-integrated electronic circuits includes: depositing an auxiliary layer on a substrate; depositing a layer of screening material on the auxiliary layer; selectively removing the layer of screening material to provide a first o... | 02/14/2006 |
| 6979526 | Lithography alignment and overlay measurement marks formed by resist mask blocking for MRAMs A method of manufacturing a resistive semiconductor memory device (10), comprising depositing an insulating layer (34) over a workpiece (30), and defining a pattern for a plurality of alignment marks (22) and a plurality of conductive lin... | 12/27/2005 |
| 6972259 | Method for forming openings in low dielectric constant material layer The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer and one or more hard mask layers is applied on the dielectric layer ... | 12/06/2005 |
| 6949444 | High-frequency line A method for forming at least one conductive line intended to receive high-frequency or high-value currents, formed above a given portion of a solid substrate outside of which are formed other elements, including the steps of digging at least one trench in the solid... | 09/27/2005 |
| 6940171 | Multi-layer dielectric and method of forming same A multiple dielectric device and its method of manufacture overlaying a semiconductor material, including a substrate, an opening relative to the substrate, the opening having an aspect ratio greater than about two, a first dielectric layer in the opening, wherein a... | 09/06/2005 |
| 6916743 | Semiconductor device and method for manufacturing thereof A semiconductor device manufacturing method that enables accurate recognition of an alignment mark and optimal formation of a buried wiring. The method includes depositing an insulation film above a semiconductor device, and then etching the insulation film to form ... | 07/12/2005 |
| 6914000 | Polishing method, polishing system and process-managing system A polishing method of the present invention is a polishing method for planarizing a film to be polished that is deposited on a wafer, and includes a step (a) of establishing a polishing rate distribution of the film to be polished that is deposited on the wafer and ... | 07/05/2005 |
| 6803308 | Method of forming a dual damascene pattern in a semiconductor device The present invention is directed to a method of forming a dual damascene pattern in a fabrication process of a semiconductor device, which is capable of simplifying a fabrication process of a semiconductor device by filling a via hole with a photoresist, using a re... | 10/12/2004 |
| 6774042 | Planarization method for deep sub micron shallow trench isolation process A method of planarizing wafers using shallow trench isolation is described. The method uses a very hard polishing pad and chemical mechanical polishing with no additional etching required. Trenches are formed in a substrate and filled with a trench dielectric, such ... | 08/10/2004 |
| 6753259 | Method of improving the bondability between Au wires and Cu bonding pads Cu, for its rather low resistivity, will be widely used in sub-quarter micron meter ULSI devices. However, it is well known that Cu is easy to be corroded as exposed in air. In packaging of chips the bonding pads making of Cu will thus oxides. In addition, the react... | 06/22/2004 |
| 6746888 | Display and fabricating method thereof A transmission type display includes a thin film transistor for driving a pixel electrode, which transistor is provided on a substrate, and a conductive shield layer provided at a position over the thin film transistor and under the pixel electrode. A first planariz... | 06/08/2004 |
| 6743724 | Planarization process for semiconductor substrates A method of manufacturing semiconductor devices using an improved chemical mechanical planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved chemical mechanical planarization process inclu... | 06/01/2004 |
| 6716739 | Bump manufacturing method A method of forming bumps on the active surface of a silicon wafer. A first under-ball metallic layer is formed over the active surface of the wafer. A second under-ball metallic layer is formed over the first under-ball metallic layer. A portion of the second under... | 04/06/2004 |
