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| Number | Title | Issue Date |
| 8173548 | Reverse planarization method A method for fabricating an integrated circuit device is disclosed. The method includes providing a substrate; forming a semiconductor feature over the substrate; forming a first photoresist layer over the substrate; performing a lithography process on the first pho... | 05/08/2012 |
| 8153528 | Surface characteristics of graphite and graphite foils The invention relates generally to preparation of a substrate for use in a photovoltaic device by application of a filling material and subsequent planarization of the top surface; optionally, a barrier layer is added. ... | 04/10/2012 |
| 8058175 | Method for planarization of wafer and method for formation of isolation structure in top metal layer The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer... | 11/15/2011 |
| 8032856 | Method and system for designing semiconductor integrated circuit providing dummy pattern in divided layout region A method of designing a semiconductor integrated circuit, includes dividing a layout area in which a wiring pattern is disposed, into a plurality of division areas, determining a dummy pattern disposition area provided in each of the plurality of division areas, add... | 10/04/2011 |
| 7989349 | Methods of manufacturing nanotubes having controlled characteristics A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further, a plurality of nanotubes may be formed generally within each of the plurality of recesses and the plurali... | 08/02/2011 |
| 7955982 | Method for smoothing wafer surface and apparatus used therefor Disclosed is a method for smoothing the surface of at least one side of a wafer which is obtained by slicing a semiconductor ingot. In this method, a fluid is applied according to projections of the wafer surface, thereby reducing the projections. Alternatively, a f... | 06/07/2011 |
| 7884021 | Planarization of a layer over a cavity A method for fabricating a micro structure includes disposing a sacrificial material in a recess formed in a lower layer and forming a layer of compensatory material on the sacrificial material in the recess. The compensatory material is higher than the upper surfac... | 02/08/2011 |
| 7838427 | Method for planarization A method of planarizing a dielectric insulating layer including providing a substrate including forming a first dielectric insulating layer having a concave and convex portion on the substrate; forming an organic resinous layer on the first dielectric insulating lay... | 11/23/2010 |
| 7749910 | Method of reducing the surface roughness of a semiconductor wafer The invention provides a method for reducing the roughness of a free surface of a semiconductor wafer that includes removing material from the free surface of the wafer to provide a treated wafer, and performing a first rapid thermal annealing on the treated wafer i... | 07/06/2010 |
| 7727894 | Formation of an integrated circuit structure with reduced dishing in metallization levels An integrated circuit structure includes a metallization level having a dual damascene trench structure formed in a layer of dielectric material. The dielectric material has an upper surface with a first degree of planarity. The metallization level includes a conduc... | 06/01/2010 |
| 7601646 | Top-oxide-early process and array top oxide planarization Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjun... | 10/13/2009 |
| 7544621 | Method of removing a metal silicide layer on a gate electrode in a semiconductor manufacturing process and etching method A method of removing a metal silicide layer on a gate electrode in a semiconductor manufacturing process is disclosed, in which the gate electrode, a metal silicide layer, a spacer, a silicon nitride cap layer, and a dielectric layer have been formed. The method inc... | 06/09/2009 |
| 7488686 | Electrochemical fabrication methods including use of surface treatments to reduce overplating and/or planarization during formation of multi-layer three-dimensional structures A method of fabricating three-dimensional structures from a plurality of adhered layers of at least a first and a second material wherein the first material is a conductive material and wherein each of a plurality of layers includes treating a surface of a first mat... | 02/10/2009 |
| 7435632 | Method for manufacturing a bottom substrate of a liquid crystal display device A method for manufacturing a bottom substrate of a liquid crystal display device by using only three masks is disclosed. The method includes the following steps. First, a patterned first metal layer, an insulating layer, a semiconductor layer and a second metal laye... | 10/14/2008 |
| 7435654 | Analog capacitor having at least three high-k dielectric layers, and method of fabricating the same There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower... | 10/14/2008 |
| 7422985 | Method for reducing dielectric overetch using a dielectric etch stop at a planar surface A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. In a preferred embodiment, the conductive or semiconductor features are pillars forming vertically oriented diodes. A second dielectric material, diffe... | 09/09/2008 |
| 7416985 | Semiconductor device having a multilayer interconnection structure and fabrication method thereof A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench formed in the first interlayer insulation film and having a sidewall s... | 08/26/2008 |
| 7413987 | Method for manufacturing a semiconductor device There is disclosed a method of manufacturing a semiconductor device, wherein an Si3N4 film is formed as a mask member on the surface of a silicon substrate, then etched to form an STI trench. A solution of perhydrogenated silazane polymer is co... | 08/19/2008 |
| 7405152 | Reducing wire erosion during damascene processing A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of unwanted material and thus, reduces unwanted erosion of certain nearby str... | 07/29/2008 |
| 7393768 | Etching of structures with high topography The present invention relates to a method for the patterning of a stack of layers on a surface with high topography. A method of the present invention can be used for gate patterning for multiple Gate FETs (MuGFETs), for patterning of the control gate in non-volatil... | 07/01/2008 |
| 7371436 | Method and apparatus for depositing materials with tunable optical properties and etching characteristics A method and system for depositing a film with tunable optical and etch resistant properties on a substrate by plasma-enhanced chemical vapor deposition. A chamber has a plasma source and a substrate holder coupled to a RF source. A substrate is placed on the substr... | 05/13/2008 |
| 7368385 | Method for producing a structure on the surface of a substrate The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method involves forming a first partial structure on the surface of the substrate, which has structure elements that a... | 05/06/2008 |
| 7361598 | Method for fabricating semiconductor device capable of preventing scratch Disclosed is a method for fabricating a semiconductor device capable of preventing scratches. The method includes the steps of: forming a substrate divided into a peripheral region and a cell region where a capacitor including a metal plate electrode on which partic... | 04/22/2008 |
| 7354527 | Chemical mechanical polishing pad and chemical mechanical polishing process A chemical mechanical polishing pad which has a storage elastic modulus E′(30° C.) at 30° C. of 120 MPa or less and an (E′(30° C.)/E′(60° C.)) ratio of the storage elastic modulus E′(30° C.) at 30° C. to the storage elastic modulus E′(60° C.) at 60Â... | 04/08/2008 |
| 7354530 | Chemical mechanical polishing systems and methods for their use Alpha-amino acid containing chemical mechanical polishing compositions and slurries that are useful for polishing substrates including multiple layers of metals, or metals and dielectrics. ... | 04/08/2008 |
| 7346981 | Method for fabricating microelectromechanical system (MEMS) devices A process for fabricating a MEMS device comprises the steps of depositing and patterning on one side of a wafer a layer of material having a preselected electrical resistivity; bonding a substrate to the one side of the wafer using an adhesive bonding agent, the sub... | 03/25/2008 |
| 7344906 | Structure and method for releasing stressy metal films A method and structure for forming a spring structure that avoids undesirable kinks in the spring is described. The method converts a portion of a release layer such that the converted portion resists etching. The converted portion then serves as an anchor region fo... | 03/18/2008 |
| 7341502 | Methods and systems for planarizing workpieces, e.g., microelectronic workpieces Planarizing workpieces, e.g., microelectronic workpieces, can employ a process indicator which is adapted to change an optical property in response to a planarizing condition. This process indicator may, for example, change color in response to reaching a particular... | 03/11/2008 |
| 7319076 | Low resistance T-shaped ridge structure A method and apparatus to provide a low resistance interconnect. A void is defined in the sacrificial layer that is proximate to an active layer. An overgrowth layer is formed in the void and over portions of the sacrificial layer adjacent to the void. A ridge secti... | 01/15/2008 |
| 7305642 | Method of tiling analog circuits The present invention provides a method for tiling an integrated circuit having a critically matched device such as a transistor. The method obtains an advantage of automatically improving metallic density over critically matched devices thus yielding improved CMP. ... | 12/04/2007 |
| 7303462 | Edge bead removal by an electro polishing process A method and apparatus for the removal of a deposited conductive layer along an edge of a substrate using an electrode configured to electro polish a substrate edge are disclosed. The electro polishing of the substrate edge may occur simultaneously during electroche... | 12/04/2007 |
| 7300595 | Method for filling concave portions of concavo-convex pattern and method for manufacturing magnetic recording medium A method for filling concave portions of a concavo-convex pattern by which the concave portions of the concavo-convex pattern can be filled to flatten the surface with reliability, and a method for manufacturing a magnetic recording medium by which a magnetic record... | 11/27/2007 |
| 7301599 | Two step maskless exposure of gate and data pads A method of fabricating a liquid crystal display device includes forming a gate line, a gate pad, and a gate electrode on a first substrate, forming a gate insulating layer on the gate line, the gate electrode, and the gate pad, forming an active layer on the gate i... | 11/27/2007 |
| 7294583 | Methods for the use of alkoxysilanol precursors for vapor deposition of SiOfilms A method for depositing conformal dielectric films uses alkoxy silanol or silanediol precursors and oxidizing and/or hydrolyzing agents. The method produces a material with liquid-like flow properties capable of achieving improved high aspect ratio gap fill more eff... | 11/13/2007 |
| 7294580 | Method for plasma stripping using periodic modulation of gas chemistry and hydrocarbon addition A method for etching a feature in a low-k dielectric layer through a photoresist etch mask over a substrate. A gas-modulated cyclic stripping process is performed for more than three cycles for stripping a single photoresist mask. Each cycle of the gas-modulated cyc... | 11/13/2007 |
| 7291561 | MEMS device integrated chip package, and method of making same The present invention relates to a chip package that includes a semiconductor device and at least one micro electromechanical structure (MEMS) such that the semiconductor device and the MEMS form an integrated package. One embodiment of the present invention include... | 11/06/2007 |
| 7282451 | Methods of forming integrated circuit devices having metal interconnect layers therein Methods of forming metal interconnect layers include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming a recess in the electrically insulating layer, at a location adjacent the contact hole. The con... | 10/16/2007 |
| 7279425 | Polishing method A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items such as slurries and polishing pads is reduced. A metal film fo... | 10/09/2007 |
| 7273563 | Method for manufacturing a magnetic recording medium A method for manufacturing a magnetic recording medium is provided, which can efficiently manufacture a magnetic recording medium that includes a recording layer formed in a concavo-convex pattern and has good recording and reproduction characteristics. The method i... | 09/25/2007 |
| 7270758 | Method to improve ability to perform CMP-assisted liftoff for trackwidth definition A method is presented for fabricating a read head having a read head sensor and a hard bias/lead layer which includes depositing a strip of sensor material in a sensor material region, and depositing strips of fast-milling dielectric material in first and second fas... | 09/18/2007 |
