Quotables
"Everyone acquainted with the subject will recognize it as a conspicuous failure."
Henry Morton, president of the Stevens Institute of Technology ; Said in 1880 about the light bulb
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8183159 | Device component forming method with a trim step prior to sidewall image transfer (SIT) processing Disclosed herein is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formati... | 05/22/2012 |
| 8183158 | Semiconductor processing apparatus and method for using same A method for using a semiconductor processing apparatus includes supplying an oxidizing gas and a reducing gas into a process container of the processing apparatus accommodating no product target substrate therein; causing the oxidizing gas and the reducing gas to r... | 05/22/2012 |
| 8178442 | Method of forming patterns of semiconductor device A method in the fabrication of a semiconductor device simultaneously forms different patterns on the same level of the device. The device has a first area and a second area. A low density mask pattern of at least one relatively wide topographic feature is formed on ... | 05/15/2012 |
| 8173547 | Silicon etch with passivation using plasma enhanced oxidation A method and apparatus for etching a silicon layer through a patterned mask formed thereon are provided. The silicon layer is placed in an etch chamber. An etch gas comprising a fluorine containing gas and an oxygen and hydrogen containing gas is provided into the e... | 05/08/2012 |
| 8158522 | Method of forming a deep trench in a substrate Methods of forming deep trenches in substrates are described. A method includes providing a substrate with a patterned film disposed thereon, the patterned film including a trench having a first width and a pair of sidewalls, the trench exposing the top surface of t... | 04/17/2012 |
| 8105951 | Method for fabricating device pattern A method for fabricating a device pattern includes the following steps. A first pattern having a first density is formed in a pre-determined region on a substrate. The first pattern includes a base portion along a first direction and at least two protruding portions... | 01/31/2012 |
| 8105950 | Method for forming fine patterns using etching slope of hard mask layer in semiconductor device A method for forming fine patterns in a semiconductor device includes forming a first hard mask layer and a second hard mask layer over an etch target layer, forming second hard mask patterns by etching the second hard mask layer, wherein an etching profile of the s... | 01/31/2012 |
| 8008204 | Method of manufacturing semiconductor device A method of manufacturing the semiconductor device is provided, which provides a prevention for a “dug” of a silicon substrate caused by the etching in regions except a region for forming a film during a removal of the film with a chemical solution. A method of ... | 08/30/2011 |
| 7968467 | Method for forming patterns in semiconductor memory device A method for forming patterns in a semiconductor memory device, wherein first spacers arranged at a first spacing and second spacers arranged at a second spacing are formed on a target layer which is formed on a semiconductor substrate. A mask pattern is formed to c... | 06/28/2011 |
| 7968466 | Fabrication process of a semiconductor device to form ultrafine patterns smaller than resolution limit of exposure apparatus A method for fabricating an electron device on a substrate includes the steps of forming a dummy film over the substrate such that the dummy film covers a device region of the substrate and an outer region of the substrate outside the device region, forming a dummy ... | 06/28/2011 |
| 7939448 | Semiconductor device having electrode and manufacturing method thereof A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semi... | 05/10/2011 |
| 7923372 | Method for fabricating semiconductor device A method for fabricating a semiconductor device includes forming a plurality of etch mask patterns over an etch target layer, each of the etch mask patterns including a first hard mask, a first pad layer, and a second pad layer, forming spacers on both sidewalls of ... | 04/12/2011 |
| 7923373 | Pitch multiplication using self-assembling materials Self-assembling materials, such as block copolymers, are used as mandrels for pitch multiplication. The copolymers are deposited over a substrate and directed to self-assemble into a desired pattern. One of the blocks forming the block copolymers is selectively remo... | 04/12/2011 |
| 7910485 | Method for forming contact hole using dry and wet etching processes in semiconductor device A method for forming a contact hole in a semiconductor device includes forming an insulation layer over a substrate, forming a hard mask pattern over the insulation layer, forming a first contact hole by partially etching the insulation layer, forming a spacer on si... | 03/22/2011 |
| 7906434 | Manufacturing method of semiconductor devices A semiconductor device manufacturing method includes: depositing a first insulating film and a second insulating film on a substrate sequentially and forming a pattern on the second insulating film; forming a silicon film on the pattern; forming a sidewall made of t... | 03/15/2011 |
| 7807575 | Methods to reduce the critical dimension of semiconductor devices A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and th... | 10/05/2010 |
| 7786013 | Method of fabricating semiconductor device The present invention relates to methods of fabricating semiconductor devices, including forming a trench in a semiconductor substrate by a reactive ion etching (RIE) method with a reactive product of film stack of a carbon film/silicon oxide film/carbon-containing ... | 08/31/2010 |
| 7772122 | Sidewall forming processes An etch layer underlying a patterned photoresist mask is provided. A plurality of sidewall forming processes are performed. Each sidewall forming process comprises depositing a protective layer on the patterned photoresist mask by performing multiple cyclical deposi... | 08/10/2010 |
| 7745337 | Method of optimizing sidewall spacer size for silicide proximity with in-situ clean A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing... | 06/29/2010 |
| 7737039 | Spacer process for on pitch contacts and related structures Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as co... | 06/15/2010 |
| 7709389 | Method of fabricating a semiconductor device A method of fabricating a semiconductor device comprising a method of forming an etching mask used for etching a semiconductor base material is disclosed. The method of fabricating a semiconductor device comprises forming hard mask patterns on a semiconductor base m... | 05/04/2010 |
| 7589024 | Process for producing semiconductor integrated circuit device Recently, with shortened wavelengths employed in aligners, it is now difficult to use a material containing a benzene ring as a photoresist material. Since resist has extremely low plasma resistance, formation of deep holes using a photoresist as a dry etching mask ... | 09/15/2009 |
| 7585773 | Non-conformal stress liner for enhanced MOSFET performance A semiconductor device is provided wherein at least one offset spacer is reduced and a non-conformal stress liner is thereafter deposited. By depositing the non-conformal stress liner in accordance with the present invention in close stress proximity to the FET, the... | 09/08/2009 |
| 7579280 | Method of patterning a film A method of patterning a thin film. The method includes forming a mask on a film to be patterned. The film is then etched in alignment with the mask to form a patterned film having a pair of laterally opposite sidewalls. A protective layer is formed on the pair of l... | 08/25/2009 |
| 7557042 | Method for making a semiconductor device with reduced spacing Floating gates are formed in two separate polysilicon depositions steps resulting in distinct portions. The first formed portions are between isolation regions. A thick insulator is formed over the isolation regions and floating gate portions. The thick insulator is... | 07/07/2009 |
| 7553769 | Method for treating a dielectric film A method and system for treating a dielectric film includes exposing at least one surface of the dielectric film to a CxHy containing material, wherein x and y are each integers greater than or equal to a value of unity. The dielectric film can... | 06/30/2009 |
| 7507669 | Gap tuning for surface micromachined structures in an epitaxial reactor A device includes a top layer having at least two opposing faces, and at least two epitaxially deposited layers, each of the at least two epitaxially deposited layers situated on a respective one of the at least two opposing faces, a combined thickness of the at lea... | 03/24/2009 |
| 7504339 | Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallog... | 03/17/2009 |
| 7491647 | Etch with striation control A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striatio... | 02/17/2009 |
| 7439143 | Flash memory device and method of manufacturing the same Disclosed is a flash memory device. The flash memory device includes a plurality of trench lines in an isolation region of a semiconductor device, a common source region along a word line (WL) direction under a surface portion of the semiconductor substrate, a plura... | 10/21/2008 |
| 7435683 | Apparatus and method for selectively recessing spacers on multi-gate devices Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed. ... | 10/14/2008 |
| 7435536 | Method to align mask patterns Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pit... | 10/14/2008 |
| 7432120 | Method for realizing a hosting structure of nanometric elements Method for manufacturing a hosting structure of nanometric elements comprising the steps of depositing on an upper surface of a substrate, of a first material, a block-seed having at least one side wall. Depositing on at least one portion of sad surface and on the b... | 10/07/2008 |
| 7432172 | Plasma etching method A plasma etching method for etching an object to be processed, which has at least an etching target layer and a patterned mask layer formed on the etching target layer, to form a recess corresponding to a pattern of the mask layer in the etching target layer, includ... | 10/07/2008 |
| 7427568 | Method of forming an interconnect structure A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the ... | 09/23/2008 |
| 7425277 | Method for hard mask CD trim Broadly speaking, methods and an apparatus are provided for removing an inorganic material from a substrate. More specifically, the methods provide for removing the inorganic material from the substrate through exposure to a high density plasma generated using an in... | 09/16/2008 |
| 7413987 | Method for manufacturing a semiconductor device There is disclosed a method of manufacturing a semiconductor device, wherein an Si3N4 film is formed as a mask member on the surface of a silicon substrate, then etched to form an STI trench. A solution of perhydrogenated silazane polymer is co... | 08/19/2008 |
| 7407890 | Patterning sub-lithographic features with variable widths A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths ... | 08/05/2008 |
| 7387927 | Reducing oxidation under a high K gate dielectric A metal layer is formed on a dielectric layer, which is formed on a substrate. After forming a masking layer on the metal layer, the exposed sides of the dielectric layer are covered with a polymer diffusion barrier. ... | 06/17/2008 |
| 7381943 | Neutral particle beam processing apparatus The present invention relates to a neutral particle beam processing apparatus. More specifically, the present invention relates to a neutral particle beam processing apparatus comprising a plasma discharging space inside which processing gases are converted to plasm... | 06/03/2008 |
