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| Number | Title | Issue Date |
| 8187974 | Methods of manufacturing semiconductor devices and optical proximity correction Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a... | 05/29/2012 |
| 8187975 | Hydrochloric acid etch and low temperature epitaxy in a single chamber for raised source-drain fabrication A raised source-drain structure is formed using a process wherein a semiconductor structure is received in a process chamber that is adapted to support both an etching process and an epitaxial growth process. This semiconductor structure includes a source region and... | 05/29/2012 |
| 8183156 | Method of etching a material surface Disclosed is a method of structuring a material surface by dry etching, so that a passivation layer soluble in a solvent forms by the dry etching on parts of the structured material surface, sealing the passivation layer with a substance soluble in the solvent, and ... | 05/22/2012 |
| 8173546 | Etchant composition, patterning conductive layer and manufacturing flat panel, display device using the same An etchant composition that allows simplification and optimization of semiconductor manufacturing process is presented, along with a method of patterning a conductive layer using the etchant and a method of manufacturing a flat panel display using the etchant. The e... | 05/08/2012 |
| 8163650 | Adjuvant for controlling polishing selectivity and chemical mechanical polishing slurry comprising the same Disclosed is an adjuvant for use in simultaneous polishing of a cationically charged material and an anionically charged material, which forms an adsorption layer on the cationically charged material in order to increase polishing selectivity of the anionically char... | 04/24/2012 |
| 8143165 | Method for fabricating semiconductor devices using strained silicon bearing material A method of manufacturing an integrated circuit on semiconductor substrates, e.g., silicon wafer. The method includes providing a semiconductor substrate characterized by a first lattice with a first structure and a first spacing. In a specific embodiment, the semic... | 03/27/2012 |
| 8143163 | Method for forming pattern of semiconductor device A method for manufacturing a semiconductor device comprises performing a CMP process using an oxide film as an etching barrier film to maintain a polysilicon layer having a large open area. A word line pattern, a DSL pattern, and a SSL pattern that are formed by a f... | 03/27/2012 |
| 8143164 | Formation of a zinc passivation layer on titanium or titanium alloys used in semiconductor processing Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprisi... | 03/27/2012 |
| 8138088 | Manufacturing method of structure by imprint A manufacturing method of a structure by an imprint process includes a first imprint step of forming a first resin material layer by applying a first resin material onto a substrate and then transferring an imprint pattern of a mold onto the first resin material lay... | 03/20/2012 |
| 8138089 | Method and apparatus for measurement and control of photomask to substrate alignment A method, structure, system of aligning a substrate to a photomask. The method comprising: directing light through a clear region of the photomask in a photolithography tool, through a lens of the tool and onto a set of at least three diffraction minor arrays on the... | 03/20/2012 |
| 8133814 | Etch methods for semiconductor device fabrication Methods are provided for fabricating a semiconductor device. One embodiment includes forming an insulator layer overlying a semiconductor substrate and depositing a layer of polycrystalline silicon overlying the insulator layer. Conductivity determining impurity ion... | 03/13/2012 |
| 8119528 | Nanoscale electrodes for phase change memory devices A process for preparing a phase change memory semiconductor device comprising a (plurality of) nanoscale electrode(s) for alternately switching a chalcogenide phase change material from its high resistance (amorphous) state to its low resistance (crystalline) state,... | 02/21/2012 |
| 8105947 | Post etch dielectric film re-capping layer Methods for improving post etch in via or trench formation in semiconductor devices. A preferred embodiment comprises forming a re-capping layer over a dielectric film following an initial etch to form a feature in the dielectric film, followed by additional etch an... | 01/31/2012 |
| 8101522 | Silicon substrate having nanostructures and method for producing the same and application thereof A method for forming a silicon substrate having a multiple silicon nanostructures includes the steps of: providing a silicon substrate; forming an oxidization layer on the silicon substrate; immersing the silicon substrate in a fluoride solution including metal ions... | 01/24/2012 |
| 8076245 | MOS low power sensor with sacrificial membrane A metal oxide semiconductor (MOS) device includes a substrate, a lower sacrificial membrane adjacent to the substrate, an upper thin film structure adjacent to the lower membrane, and a MOS material deposited on the upper thin film structure. ... | 12/13/2011 |
| 8076244 | Methods for causing fluid to flow through or into via holes, vents and other openings or recesses that communicate with surfaces of substrates of semiconductor device components A method for removing material from surfaces of at least a portion of at least one recess or at least one aperture extending into a surface of a substrate includes pressurizing fluid so as to cause the fluid to flow into the at least one recess or at least one apert... | 12/13/2011 |
| 8048806 | Methods to avoid unstable plasma states during a process transition In some implementations, a method is provided in a plasma processing chamber for stabilizing etch-rate distributions during a process transition from one process step to another process step. The method includes performing a pre-transition compensation of at least o... | 11/01/2011 |
| 8048807 | Method and apparatus for thinning a substrate Provided is a method for fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a backside, where active or passive devices are formed in the front side, rotating the semiconductor substrate, and etching the back... | 11/01/2011 |
| 8030213 | Polishing compound for semiconductor integrated circuit device, polishing method and method for producing semiconductor integrated circuit device To provide a polishing technique with which in production of a semiconductor integrated circuit device, when a plane to be polished is polished, an appropriate polishing rate ratio of a polysilicon film to another material can be obtained, whereby high level planari... | 10/04/2011 |
| 8026175 | Cleaning apparatus of semiconductor substrate and method of manufacturing semiconductor device After a liquid chemical treatment is finished, in parallel with a washing away treatment and/or a drying treatment, by spraying from a nozzle for a cleaning liquid supplied by a cleaning line to an outer surface of a nozzle for a liquid chemical, crystals and the li... | 09/27/2011 |
| 8012877 | Backside nitride removal to reduce streak defects Exemplary embodiments provide a method for fabricating an integrated circuit (IC) device with reduced streak defects. In one embodiment, the IC device structure can be formed having a first pad oxide-based layer on a front side of a semiconductor substrate and havin... | 09/06/2011 |
| 7985681 | Method for selectively forming symmetrical or asymmetrical features using a symmetrical photomask during fabrication of a semiconductor device and electronic systems including the semiconductor device A method for patterning a material during fabrication of a semiconductor device provides for the selective formation of either asymmetrical features or symmetrical features using a symmetrical photomask, depending on which process flow is chosen. The resulting featu... | 07/26/2011 |
| 7981800 | Shallow trench isolation structures and methods for forming the same A shallow trench isolation (STI) structure and method for forming the same is provided that reduces defects in a nitride film used as a field oxide mask and variations in pad oxide thickness. Generally, the method involves depositing a nitride over pad oxide on a su... | 07/19/2011 |
| 7955981 | Method of making a two-terminal non-volatile memory pillar device with rounded corner A non-volatile memory device includes a plurality of pillars, where each of the plurality of pillars contains a non-volatile memory cell containing a steering element and a storage element and at least one of a top corner or a bottom corner of each of the plurality ... | 06/07/2011 |
| 7943519 | Etchant, method for fabricating interconnection line using the etchant, and method for fabricating thin film transistor substrate using the etchant An etchant, a method for fabricating a multi-layered interconnection line using the etchant, and a method for fabricating a thin film transistor (TFT) substrate using the etchant. The etchant for the multi-layered line comprised of molybdenum/copper/molybdenum nitri... | 05/17/2011 |
| 7935635 | Method of forming fine patterns of semiconductor devices using double patterning A method of forming fine patterns of semiconductor device according to an example embodiment may include forming a plurality of multi-layered mask patterns by stacking first mask patterns and buffer mask patterns on an etch film to be etched on a substrate, forming,... | 05/03/2011 |
| 7935634 | Integrated circuits, micromechanical devices, and method of making same A method of making an integrated circuit comprises providing a substrate and forming a structure on the substrate comprising a first enclosed portion of a carbon material and a second portion of the carbon material, wherein an intersection of the first and second po... | 05/03/2011 |
| 7935633 | Poly etch without separate oxide decap The use of an ammonium hydroxide spike to a hot tetra methyl ammonium hydroxide (TMAH) solution to form an insitu poly oxide decapping step in a polysilicon (poly) etch process, results in a single step rapid poly etch process having uniform etch initiation and a hi... | 05/03/2011 |
| 7932181 | Edge gas injection for critical dimension uniformity improvement A method of etching a semiconductor substrate with improved critical dimension uniformity comprises supporting a semiconductor substrate on a substrate support in an inductively coupled plasma etch chamber; supplying a first etch gas to a central region over the sem... | 04/26/2011 |
| 7915168 | Semiconductor processing methods Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the ... | 03/29/2011 |
| 7915167 | Fabrication of channel wraparound gate structure for field-effect transistor A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed b... | 03/29/2011 |
| 7910483 | Trim process for critical dimension control for integrated circuits Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer o... | 03/22/2011 |
| 7910482 | Method of forming a finFET and structure A method for processing a substrate comprising at least a buried oxide (BOX) layer and a semiconductor material layer is provided. The method includes etching the semiconductor material layer to form a vertical semiconductor material structure overlying the BOX laye... | 03/22/2011 |
| 7884020 | Polishing cloth and method of manufacturing semiconductor device A polishing cloth used in the chemical mechanical polishing treatment comprises a molded body of (meth)acrylic copolymer having an acid value of 10 to 100 mg KOH/g and a hydroxyl group value of 50 to 150 mg KOH/g. ... | 02/08/2011 |
| 7871932 | Manufacturing method of semiconductor device In the semiconductor device manufacturing method of the present invention, first, the emissivity of a wafer placed in a chamber is measured. Then, the fluctuation rate of a wafer physical quantity that fluctuates in association with the given thermal energy is calcu... | 01/18/2011 |
| 7871931 | Method for chemical mechanical planarization of a metal layer located over a photoresist layer and a method for manufacturing a micro pixel array using the same The present invention provides a method for planarizing a metal layer, and a method for manufacturing a micro pixel array. The method for planarizing the metal layer, without limitation, may include the steps of forming a metal layer over a photoresist layer, and th... | 01/18/2011 |
| 7867908 | Method of fabricating substrate A method of fabricating a substrate includes following steps. First, a metallic panel having a first surface and a second surface is provided. A first half-etching process is carried out to etch the first surface of the metallic panel to a first depth so that a firs... | 01/11/2011 |
| 7867907 | Method for manufacturing semiconductor device The present invention provides a method by which a thin film process can be conducted simply and accurately without using resist. Further, the present invention provides a method of manufacturing semiconductor devices at low cost. A first layer is formed over a subs... | 01/11/2011 |
| 7858526 | Method of patterning gate electrodes by reducing sidewall angles of a mask layer By performing an anisotropic resist modification prior to the actual resist trimming process, the profile of the end portions of the resist features may be significantly enhanced, for instance by providing substantially vertical sidewall portions. Consequently, an o... | 12/28/2010 |
| 7838424 | Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching An improved Wafer-Level Chip-Scale Packaging (WLCSP) process is described that includes forming a plurality of conductive pillars on a first surface of a semiconductor wafer. One or more grooves are dry etched into the first surface of the semiconductor wafer, where... | 11/23/2010 |
