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| Number | Title | Issue Date |
| 8110504 | Method of manufacturing semiconductor device The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insul... | 02/07/2012 |
| 8062978 | Crystalline aluminum oxide layers having increased energy band gap, charge trap layer devices including crystalline aluminum oxide layers, and methods of manufacturing the same Crystalline aluminum oxide layers having increased energy band gap, charge trap memory devices including crystalline aluminum oxide layers and methods of manufacturing the same are provided. A method of forming an aluminum oxide layer having an increased energy band... | 11/22/2011 |
| 8003536 | Electromigration resistant aluminum-based metal interconnect structure A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevat... | 08/23/2011 |
| 7871930 | Method of manufacturing a light emitting device and thin film forming apparatus A method of manufacturing a light emitting device is provided in which satisfactory image display can be performed by the investigation and repair of short circuits in defect portions of light emitting elements. A backward direction electric current flows in the def... | 01/18/2011 |
| 7488684 | Organic aluminum precursor and method of forming a metal wire using the same An organic aluminum precursor includes aluminum as a central metal, and borohydride and trimethylamine as ligands. In a method of forming an aluminum layer or wire, the organic aluminum presursor is introduced onto a substrate, and then thermally decomposed. The alu... | 02/10/2009 |
| 7473644 | Method for forming controlled geometry hardmasks including subresolution elements Methods for forming accurate, symmetric cross-section spacers of hardmask material on a substrate such as a silicon wafer or quartz substrate, for formation of precise subresolution features useful for forming integrated circuits. The resulting symmetrical hardmask ... | 01/06/2009 |
| 7432203 | Methods for fabricating a metal layer pattern Semiconductor devices and methods of fabricating the same are disclosed. An illustrated semiconductor device fabricating method includes forming a titanium and titanium-nitride (Ti/TiN) metal layer on a lower oxide layer; forming an aluminum metal layer on the Ti/Ti... | 10/07/2008 |
| 7425765 | Zinc-aluminum solder alloy A high melting point solder alloy superior in oxidation resistance, in particular a solder alloy provided with both a high oxidation resistance and high melting point suitable for filling fine through holes of tens of microns in diameter and high aspect ratios and f... | 09/16/2008 |
| 7416932 | Power composite integrated semiconductor device and manufacturing method thereof A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for reducing ON-resistance. Furthermore, wire bonding connection of the copper... | 08/26/2008 |
| 7402519 | Interconnects having sealing structures to enable selective metal capping layers Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which... | 07/22/2008 |
| 7381645 | Method for the production of an integrated circuit bar arrangement comprising a metal nitride layer and integrated circuit arrangement The document explains, inter alia, a method in which a titanium nitride layer is removed by wet chemical means (106). Following removal of the titanium nitride, further metalization strata are produced (114). The result is an integrated circuit arrange... | 06/03/2008 |
| 7378002 | Aluminum sputtering while biasing wafer An aluminum sputtering process including RF biasing the wafer and a two-step aluminum fill process and apparatus used therefor to fill aluminum into a narrow via hole by sputtering under two distinctly different conditions, preferably in two different plasma sputter... | 05/27/2008 |
| 7368014 | Variable temperature deposition methods A deposition method may include, at a first temperature, contacting a substrate with a first precursor and chemisorbing a first layer at least one monolayer thick over the substrate. At a second temperature different from the first temperature, the first layer may b... | 05/06/2008 |
| 7364832 | Wet developable hard mask in conjunction with thin photoresist for micro photolithography A novel process for using a hard mask or protective layer in conjunction with an extremely thin photoresist is provided. In this process, a thin film of the protective layer is coated on the surface of a substrate that is to be selectively modified by reactive ion e... | 04/29/2008 |
| 7361548 | Methods of forming a capacitor using an atomic layer deposition process Methods for forming a capacitor using an atomic layer deposition process include providing a reactant including an aluminum precursor onto a substrate to chemisorb a portion of the reactant to a surface of the substrate. The substrate has an underlying structure inc... | 04/22/2008 |
| 7361991 | Closed air gap interconnect structure A closed air gap interconnect structure is described. The structure includes discrete regions of a permanent support dielectric under the interconnect lines so that the lines are substantially surrounded by air except for the discrete regions of the support dielectr... | 04/22/2008 |
| 7358195 | Method for fabricating liquid crystal display device In etching a metal line formed as a dual layer of aluminum alloy and molybdenum, the metal line consisting of the dual layer of aluminum alloy and molybdenum is etched through one-time wet etching by applying the etchant including HNO3, HClO4, ... | 04/15/2008 |
| 7351650 | Post passivation interconnection schemes on top of the IC chips A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over... | 04/01/2008 |
| 7348210 | Post bump passivation for soft error protection A structure and a method for forming the same. The method includes (a) providing a structure which includes (i) a dielectric layer, (ii) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface, (iii) a first passiv... | 03/25/2008 |
| 7344986 | Plating solution, semiconductor device and method for manufacturing the same The present invention relates to a plating solution useful for forming embedded interconnects by embedding a conductive material in fine recesses for interconnects provided in the surface of a substrate, such as a semiconductor substrate, or for forming a protective... | 03/18/2008 |
| 7341942 | Method for forming metal line of semiconductor device A method for forming a metal line of a semiconductor device forms an aluminum line having an excellent orientation. A specific resistance of a metal line is reduced, thereby enabling sufficient supply of a desired electric current. The method includes steps of formi... | 03/11/2008 |
| 7335514 | Optical biosensor The present invention relates to an optical biosensor comprising a porous matrix. In the specific case, reference is made to anodized porous alumina, on the surface of which the biological component specific for the analyte in question is immobilized, and to an opti... | 02/26/2008 |
| 7329602 | Wiring structure for integrated circuit with reduced intralevel capacitance A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated fr... | 02/12/2008 |
| 7329365 | Etchant composition for indium oxide layer and etching method using the same An etchant for removing an indium oxide layer includes sulfuric acid as a main oxidizer, an auxiliary oxidizer such as H3PO4, HNO3, CH3COOH, HClO4, H2O2, and a Compound A that is obtained b... | 02/12/2008 |
| 7320942 | Method for removal of metallic residue after plasma etching of a metal layer A method for removal of metallic residue from a substrate after a plasma etch process in a semiconductor substrate processing system by cleaning the substrate in a hydrogen fluoride solution. ... | 01/22/2008 |
| 7312152 | Lactate-containing corrosion inhibitor The corrosion of aluminum-based metal films may be minimized by applying a lactate-containing solution to the aluminum-based metal films before the aluminum-based metal films are etched. The lactate-containing solution is applied to the aluminum-based metal film bef... | 12/25/2007 |
| 7301190 | Structures and methods to enhance copper metallization Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a meta... | 11/27/2007 |
| 7297640 | Method for reducing argon diffusion from high density plasma films A two-step high density plasma-CVD process is described wherein the argon content in the film is controlled by using two different argon concentrations in the argon/silane/oxygen gas mixture used for generating the high density plasma. The first step deposition uses... | 11/20/2007 |
| 7288442 | Method for manufacturing contact structures of wirings First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 m... | 10/30/2007 |
| 7285196 | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical resistance and better reliability at smaller dimensions than aluminum. However, use of copper typically requir... | 10/23/2007 |
| 7282744 | III-nitride optoelectronic device structure with high Al AlGaN diffusion barrier A III-nitride electronic device structure including doped material, an active region and a barrier material arranged to suppress transport of dopant from the doped material into the active region, wherein the barrier material comprises high-Al content Alx... | 10/16/2007 |
| 7282452 | Etching method, semiconductor and fabricating method for the same An organic/inorganic hybrid film represented by SiCx−HyOz (x>0, y≧0, z>0) is plasma-etched with an etching gas containing fluorine, carbon and nitrogen. During the etching, a carbon component is eliminated from the surface portio... | 10/16/2007 |
| 7282445 | Multiple seed layers for interconnects One embodiment of the present invention is a method for depositing two or more seed layers over a substrate, the substrate includes a patterned insulating layer which comprises at least one opening surrounded by a field, the at least one opening and the field being ... | 10/16/2007 |
| 7276434 | Method for filling a contact hole having a small diameter and a large aspect ratio A method for manufacturing a semiconductor device having a semiconductor substrate with a contact hole filled by an aluminum-containing thin film. This manufacturing method includes a step of forming a silicon-containing thin film in a region having a predetermined ... | 10/02/2007 |
| 7276795 | Small grain size, conformal aluminum interconnects and method for their formation A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mi... | 10/02/2007 |
| 7276422 | Post passivation interconnection schemes on top of the IC chips A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over... | 10/02/2007 |
| 7265047 | Post passivation interconnection schemes on top of the IC chips A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over... | 09/04/2007 |
| 7262130 | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have... | 08/28/2007 |
| 7262135 | Methods of forming layers The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zir... | 08/28/2007 |
| 7262505 | Selective electroless-plated copper metallization Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on... | 08/28/2007 |
