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| Number | Title | Issue Date |
| 8153522 | Patterning mask and method of formation of mask using step double patterning A method of forming a mask for use in fabricating an integrated circuit includes forming first non-removable portions of a photoresist material through a mask having a plurality of apertures, shifting the mask, forming second non-removable second portions of the pho... | 04/10/2012 |
| 8143160 | Method of forming a contact plug of a semiconductor device In a method of forming a contact plug of a semiconductor device, a nitride layer is prevented from being broken by forming a passivation layer over the nitride layer when contact holes are formed by etching an insulating layer between select lines formed over a semi... | 03/27/2012 |
| 8129276 | Void sealing in a dielectric material of a contact level of a semiconductor device comprising closely spaced transistors In sophisticated semiconductor devices, a contact structure may be formed on the basis of a void positioned between closely spaced transistor elements wherein disadvantageous metal migration along the void may be suppressed by sealing the voids after etching a conta... | 03/06/2012 |
| 8114773 | Cleaning solution, cleaning method and damascene process using the same A cleaning solution is provided. The cleaning solution includes (a) 0.01-0.1 wt % of hydrofluoric acid (HF); (b) 1-5 wt % of a strong acid, wherein the strong acid is an inorganic acid; (c) 0.05-0.5 wt % of ammonium fluoride (NH4F); (d) a chelating agent ... | 02/14/2012 |
| 8067312 | Coaxial through chip connection An integrated circuit chip includes devices formed by doping of a semiconductor on a substrate and at least one post-device formation through-chip via made up of an annulus of insulating material, an annulus of metallization bounding an outer surface of the annulus ... | 11/29/2011 |
| 8053365 | Methods for forming all tungsten contacts and lines Novel low-resistivity tungsten film stack schemes and methods for depositing them are provided. The film stacks include a mixed tungsten/tungsten-containing compound (e.g., WC) layer as a base for deposition of tungsten nucleation and/or bulk layers. According to va... | 11/08/2011 |
| 8048804 | Method of manufacturing semiconductor package A method of manufacturing a semiconductor package, including at least a step A that forms a first transforming portion by irradiating a laser beam on at least a portion of a first substrate; a step B that joins together the first substrate and a second substrate in ... | 11/01/2011 |
| 8026174 | Sequential station tool for wet processing of semiconductor wafers Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wa... | 09/27/2011 |
| 8008197 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device includes forming in order a barrier film, an insulating film, a first mask, and a second mask having etching properties different from those of the first mask on a substrate, removing the insulating film, the first m... | 08/30/2011 |
| 7998863 | High efficiency solar cell fabrication A method of forming a contact structure and a contact structure so formed is described. The structure contacts an underlying layer of a semiconductor junction, wherein the junction comprises the underlying layer of a semiconductor material and is separated from an o... | 08/16/2011 |
| 7981798 | Method of manufacturing substrate The present disclosure relates to a method of manufacturing a substrate. The method includes: (a) forming through holes by applying an anisotropic etching to a silicon substrate from a first surface of the silicon substrate; (b) forming a first insulating film to co... | 07/19/2011 |
| 7981797 | Phase-change random access memory device and method of manufacturing the same A method of manufacturing a phase-change random access memory device includes forming an interlayer insulating film on a semiconductor substrate, on which a bottom structure is formed, and patterning the interlayer insulating film to form a contact hole, forming a s... | 07/19/2011 |
| 7906431 | Semiconductor device fabrication method Methods of fabricating a semiconductor device including a through-silicon via that is electrically insulated from the semiconductor substrate. An exemplary method includes preparing a semiconductor wafer including a semiconductor substrate, a semiconductor element, ... | 03/15/2011 |
| 7892974 | Method of forming vias in silicon carbide and resulting devices and circuits A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon... | 02/22/2011 |
| 7892975 | Method for selectively forming electric conductor and method for manufacturing semiconductor device A method for selectively forming an electric conductor, the method including disposing a processing target and a metal compound in an atmosphere including a supercritical fluid, the processing target having formed thereon at least one recess for providing an electri... | 02/22/2011 |
| 7875553 | Method of manufacturing semiconductor package A method of manufacturing a semiconductor package, including at least a step A that forms a first transforming portion by irradiating a laser beam on at least a portion of a first substrate; a step B that joins together the first substrate and a second substrate in ... | 01/25/2011 |
| 7867903 | Passivated thin film and method of producing same A method of producing a passivated thin film material is disclosed wherein an insulating thin film layer (10), having pinholes (12) therein, is positioned upon an underlying electrically conductive substrate (11). The thin film layer is then ele... | 01/11/2011 |
| 7816265 | Method for forming vias in a substrate A method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate ... | 10/19/2010 |
| 7816264 | Wafer processing method A wafer processing method having a step of reducing the thickness of a wafer in only a device forming area where semiconductor chips are formed by grinding and etching the back side of the wafer to thereby form a recess on the back side of the wafer. At the same tim... | 10/19/2010 |
| 7790615 | Electronic component packaging The invention relates to a method to seal a cavity, comprising a hole (6), comprising: the deposition on at least part of the cover, or an electrically conductive material (4, 5), the conveyance of pa... | 09/07/2010 |
| 7772119 | Dual liner capping layer interconnect structure A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under ... | 08/10/2010 |
| 7704882 | Semiconductor devices using fine patterns and methods of forming fine patterns Example embodiments may provide fine patterns for semiconductor devices and methods of forming fine patterns for semiconductor devices. Example methods may include forming a spacer pattern on a substrate and/or an insulating layer pattern adjacent to sides of the sp... | 04/27/2010 |
| 7700484 | Method and apparatus for a metallic dry-filling process An iPVD system is programmed to deposit uniform material, such as a metallic material, into high aspect ratio nano-sized features on semiconductor substrates using a process that enhances the feature filling compared to the field deposition, while maximizing the siz... | 04/20/2010 |
| 7674712 | Patterning method for light-emitting devices A method of patterning a substrate by mechanically locating a first masking film over the substrate; removing one or more first opening portions in first locations in the first masking film to form one or more first masking portions in the first masking film. First ... | 03/09/2010 |
| 7670950 | Copper metallization of through silicon via A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate comprising immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition comprising a source of copper ... | 03/02/2010 |
| 7659202 | Triaxial through-chip connection A method performed on a wafer having multiple chips each including a doped semiconductor and substrate involves etching an annulus trench, metalizing an inner and an outer perimeter side wall of the annulus trench, etching a via trench into the wafer, making a lengt... | 02/09/2010 |
| 7645701 | Silicon-on-insulator structures for through via in silicon carriers A silicon-on-insulator (SOI) structure is provided for forming through vias in a silicon wafer carrier structure without backside lithography. The SOI structure includes the silicon wafer carrier structure bonded to a silicon substrate structure with a layer of buri... | 01/12/2010 |
| 7615490 | Method for fabricating landing plug of semiconductor device A method of fabricating a landing plug of a semiconductor device includes performing a double patterning process to separately form a landing plug contact hole for a storage node and a landing plug contact hole for a bit line, thereby facilitating forming a device h... | 11/10/2009 |
| 7608538 | Formation of vertical devices by electroplating The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level d... | 10/27/2009 |
| 7576003 | Dual liner capping layer interconnect structure and method A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under ... | 08/18/2009 |
| 7576004 | Semiconductor chip and method of manufacturing semiconductor chip A semiconductor chip includes a semiconductor substrate having a first principal surface, and having a device layer on the first principal surface in which a semiconductor device is formed, an electrode pad disposed on the first principal surface of the semiconducto... | 08/18/2009 |
| 7563714 | Low resistance and inductance backside through vias and methods of fabricating same A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; f... | 07/21/2009 |
| 7501342 | Device having high aspect-ratio via structure in low-dielectric material and method for manufacturing the same A method for manufacturing a device having a via structure includes the following steps. A seed metallic layer is formed on a substrate. A patterned metallic-trace layer is formed on the seed metallic layer. A positive-type photoresist layer is formed on the pattern... | 03/10/2009 |
| 7485577 | Method of forming metal line stacking structure in semiconductor device The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on a lower dielectric layer that is disposed over a semiconductor substr... | 02/03/2009 |
| 7485578 | Semiconductor device Embodiments relate to a semiconductor device and a method of fabricating semiconductor device, that may uniformly form a barrier layer in a via hole to thus prevent layers from being broken. In embodiments, a method of fabricating a semiconductor device may include ... | 02/03/2009 |
| 7482272 | Through chip connection A method of forming an electrically conductive path through a portion of a semiconductor material, wherein the semiconductor material abuts a substrate and wherein the semiconductor material comprises multiple electronic devices, involves forming an annular trench i... | 01/27/2009 |
| 7470620 | Microcircuit fabrication and interconnection Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to elec... | 12/30/2008 |
| 7470619 | Interconnect with high aspect ratio plugged vias Described is a method for forming a stackable interconnect. The interconnect is formed by depositing a first contact on a substrate; depositing a seed layer (SL) on the substrate; depositing a metal mask layer (MML) on the SL; depositing a bottom anti-reflection coa... | 12/30/2008 |
| 7465663 | Semiconductor device fabrication method In fabrication of a semiconductor device which is provided with resistances and MOS transistors on the same substrate, conduction failures of contacts and leaching of wiring metal into a silicon substrate is prevented. Firstly, an underlying structure is prepared. T... | 12/16/2008 |
| 7452808 | Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface laye... | 11/18/2008 |
