Celebrity Inventors
Glam girl Heddy Lamar may have used her good looks to good effect on the silver screen, but she put her smarts to better use as an inventor. During World War II, she co-patented a frequency-switching system for torpedo guidance that was considered years ahead of its time.
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| Number | Title | Issue Date |
| 8062976 | Low cost method of fabrication of vertical interconnections combined to metal top electrodes A method is for forming a vertical interconnection through a dielectric layer between upper and lower electrically conductive layers of an integrated circuit. The method includes forming an opening through the dielectric layer and placing a solidifiable electrically... | 11/22/2011 |
| 7855146 | Photo-focus modulation method for forming transistor gates and related transistor devices A method for forming a transistor gate includes performing a first exposure of a photo-resist material on a semiconductor device. The first exposure defines a line pattern in the photo-resist material. The method also includes performing a second exposure of the pho... | 12/21/2010 |
| 7566660 | Semiconductor device and method for manufacturing the same A method for manufacturing a semiconductor device includes the steps of: forming a gate on a semiconductor substrate; sequentially stacking a first oxide layer, a nitride layer and a second oxide layer on the semiconductor substrate including the gate; forming a fir... | 07/28/2009 |
| 7507663 | Fabrication of semiconductor devices Fabrication of microelectronic devices is accomplished using a substrate having a recessed pattern. In one approach, a master form is used to replicate a substrate having a pit pattern. In another approach, the substrate is produced by etching. A series of stacked l... | 03/24/2009 |
| 7439132 | Semiconductor device comprising capacitor and method of fabricating the same A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. ... | 10/21/2008 |
| 7432190 | Semiconductor device and manufacturing method thereof to prevent a notch A method for manufacturing a semiconductor device includes: preparing a substrate in which a first interlayer insulation layer having a first via hole and a first trench is formed; forming a first via plug and a first metal line by filling the first via hole and the... | 10/07/2008 |
| 7432192 | Post ECP multi-step anneal/Htreatment to reduce film impurity A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a f... | 10/07/2008 |
| 7427564 | Method for forming storage node contact plug in semiconductor device A method for forming a storage node contact plug in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer over a substrate having a conductive plug; etching a portion of the inter-layer insulation layer using at least line ... | 09/23/2008 |
| 7413977 | Method of manufacturing semiconductor device suitable for forming wiring using damascene method A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. Then a first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. Then conductive... | 08/19/2008 |
| 7410897 | Contact plug processing and a contact plug A semiconductor device has anisotropically formed via holes through a PMD layer. The anisotropic geometry of the via holes results in the diameter of a via hole over a gate structure being equal to the diameter of a via hole not over the gate structure. The via hole... | 08/12/2008 |
| 7396765 | Method of fabricating a liquid crystal display device A method of fabricating a liquid crystal display device according to an embodiment of the present invention includes forming first and second conductive layers on a substrate, wherein the first layer is transparent; patterning the second conductive layer and the fir... | 07/08/2008 |
| 7390741 | Method for fabricating semiconductor device A method for fabricating a semiconductor device comprises the steps of: forming interconnection grooves 38 in an inter-layer insulation film 34; forming an interconnection layer 44 of Cu as the main material in the interconnection grooves 38 | 06/24/2008 |
| 7368385 | Method for producing a structure on the surface of a substrate The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method involves forming a first partial structure on the surface of the substrate, which has structure elements that a... | 05/06/2008 |
| 7365020 | Method for etching upper metal of capacitator A method for etching an upper metal film of a capacitor, enables a safe etching of the upper metal film of a capacitor by exploiting an over-etch step. The method for etching the upper metal film of the capacitor includes the steps of forming a lower metal film, a l... | 04/29/2008 |
| 7354856 | Method for forming dual damascene structures with tapered via portions and improved performance The manufacture of damascene structures having improved performance, particularly, but not by way of limitation, dual damascene structures is provided. In one embodiment, a substrate having a conductive layer is formed in a first insulating layer. A protective layer... | 04/08/2008 |
| 7335593 | Method of fabricating semiconductor device A gate metal is formed in a film, the foregoing gate metal is partially etched per each TFT having a different property, and a gate electrode is fabricated. Specifically, a resist mask is fabricated by exposing a resist to light per each TFT having a different prope... | 02/26/2008 |
| 7329949 | Packaged microelectronic devices and methods for packaging microelectronic devices Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second ... | 02/12/2008 |
| 7319067 | Method of simultaneously controlling ADI-AEI CD differences of openings having different sizes and etching process utilizing the same method A method of simultaneously controlling the ADI-AEI CD differences of openings having different sizes is disclosed. The openings are formed by: forming an ARC and a photoresist layer with a first and a second opening patterns of different sizes therein on a material ... | 01/15/2008 |
| 7303945 | Method for forming pattern of stacked film and thin film transistor A method for forming a pattern of a stacked film, includes steps (a) to (e). The step (a) is forming sequentially a first base insulating film and a light shielding material on a transparent substrate. The step (b) is patterning the light shielding material to obtai... | 12/04/2007 |
| 7294572 | Method of forming contact A method of forming a contact is provided. A substrate having at least two conductive devices is provided. A spacing is located between the two conductive devices. A first dielectric layer is formed over the substrate to cover the two conductive devices and the spac... | 11/13/2007 |
| 7288477 | Electro-luminescence device including a thin film transistor and method of fabricating an electro-luminescence device An electro-luminescence device including an electro-luminescence element and a thin film transistor electrically connected to the electro-luminescence element. The thin film transistor includes a gate electrode formed over a substrate, an insulating layer formed ove... | 10/30/2007 |
| 7262065 | Ferroelectric memory and its manufacturing method A method for manufacturing a ferroelectric memory includes: (a) forming first and second contact sections on a first dielectric layer formed above a base substrate; (b) forming a laminated body having a lower electrode, a ferroelectric layer and an upper electrode s... | 08/28/2007 |
| 7247554 | Method of making integrated circuits using ruthenium and its oxides as a Cu diffusion barrier The present invention generally relates to methods used for fabricating integrated circuits (“ICs”), using Ruthenium (“Ru”) and its oxides and/or Iridium (“Ir”) and its oxides as the diffusion barrier to contain and control copper (“Cu”) interconnect... | 07/24/2007 |
| 7212699 | Fabricating a photonic die In one embodiment, a method includes forming an array of recesses in a substrate, depositing spacer material in the recesses, forming photonic elements on the spacer material, and separating the structure previously formed into individual dies that each include a ph... | 05/01/2007 |
| 7199043 | Method of forming copper wiring in semiconductor device Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing proces... | 04/03/2007 |
| 7176078 | Nonvolatile semiconductor memory device having strap region and fabricating method thereof In a nonvolatile semiconductor memory device having a memory cell array region and a strap region for providing voltage to the memory cell array region, in the memory cell array region, a plurality of word lines and a plurality of source lines are formed in a row di... | 02/13/2007 |
| 7172931 | Manufacturing method for semiconductor device It is an object of the present invention to enhance a selection ratio in an etching process, and provide a method for manufacturing a semiconductor device that has favorable uniform characteristic with high yield. In a method for manufacturing a semiconductor device... | 02/06/2007 |
| 7157370 | Semiconductor device and method for manufacturing the same A semiconductor device includes a highly reliable multi-level interconnect structure having a low effective dielectric constant and which can be easily manufactured with a relatively inexpensive process, and a method for manufacturing the semiconductor device. The s... | 01/02/2007 |
| 7101798 | Method to modulate etch rate in SLAM Several techniques are described for modulating the etch rate of a sacrificial light absorbing material (SLAM) by altering its composition so that it matches the etch rate of a surrounding dielectric. This is particularly useful in a dual damascene process where the... | 09/05/2006 |
| 7101786 | Method for forming a metal line in a semiconductor device Provided is a method for forming a metal line in a semiconductor device. The method forms round portions at top edges of an insulation film by means of a polymer and then etches the rest portion (i.e., sidewall parts) in an almost vertical direction, which makes it ... | 09/05/2006 |
| 7094672 | Method for forming self-aligned contact in semiconductor device A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method includes the steps of forming a first insulating layer that includes a nitride along a profile of a gate structure and a juncti... | 08/22/2006 |
| 7078339 | Method of forming metal line layer in semiconductor device The present invention is provided to form a metal line layer in a semiconductor device, wherein at least one conductive layer of a plurality of conductive layers is etched, a side wall oxide film is formed on side walls of some conductive layers of the etched conduc... | 07/18/2006 |
| 7052952 | Method for forming wire line by damascene process using hard mask formed from contacts A method for forming a wire line by a damascene process includes forming a first insulating layer on a semiconductor substrate, etching the first insulating layer to form a contact hole, and forming a first conductive layer over the first insulating layer that fills... | 05/30/2006 |
| 7041598 | Directional ion etching process for patterning self-aligned via contacts The invention provides a directional ion etching process to pattern self-aligned via contacts in the manufacture of semiconductor devices such as high density magnetic random access memory (MRAM). In a particular embodiment, a semiconductor wafer is prepared with ve... | 05/09/2006 |
| 7041597 | Semiconductor device having void free contact and method for fabricating the contact The present invention relates to a semiconductor device and a method for fabricating a contact of the semiconductor device, and in particular, to the method for fabricating a semiconductor contact of the device for electrically coupling upper and lower metal wires o... | 05/09/2006 |
| 7029936 | Semiconductor laser, device having reduced contact resistance and manufacturing method thereof A semiconductor laser element capable of reducing the contact resistance and the thermal resistance and realizing a high reliability is provided. The semiconductor laser element includes: a semiconductor substrate, an active layer formed on the semiconductor substra... | 04/18/2006 |
| 7030016 | Post ECP multi-step anneal/H2 treatment to reduce film impurity A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a f... | 04/18/2006 |
| 7026239 | Method for making an anisotropic conductive polymer film on a semiconductor wafer A method of manufacturing an anisotropic conductive polymer film on a semiconductor wafer including on one surface a layer of passivation in which at least one opening is made to allow access to a contact pad. The method can be applied to creating components (chips,... | 04/11/2006 |
| 7018922 | Patterning for elongated Vcontact flash memory A method of forming a contact in a flash memory device is disclosed. The method increases the depth of focus margin and the overlay margin between the contact and the stacked gate layers. A plurality of stacked gate layers are formed on a semiconductor substrate, wh... | 03/28/2006 |
| 6989282 | Control of liner thickness for improving thermal cycle reliability A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold ... | 01/24/2006 |
