Did You Know...
...that one person who claimed to be the inventor of the television is Russian emigre Vladimir Zworykin? In 1929 David Sarnoff, founder of RCA, asked Zworykin what it would take to develop TV for commercial use. He said: a year and a half and $100,000. In reality, it took 20 years and $50 million! Before his death in 1982 at the age of 92, Zworykin said of his invention: "The technique is wonderful. It is beyond my expectations. But the programs! I would never let my children even come close to this thing."
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| Number | Title | Issue Date |
| 8071475 | Liner for tungsten/silicon dioxide interface in memory A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard ... | 12/06/2011 |
| 8058169 | Interconnection architecture for semiconductor device An interconnection architecture, for a semiconductor device (having regions arranged to include at least an inner region, an intermediate region located at least aside the inner region, and an outer region located at least on a side of the intermediate region opposi... | 11/15/2011 |
| 7985678 | Method of manufacturing a semiconductor integrated circuit device In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately ... | 07/26/2011 |
| 7943515 | Shared masks for x-lines and shared masks for y-lines for fabrication of 3D memory arrays A structure and a method of manufacturing a three dimensional memory using a number of bit line masks that is less than the number of device layers. A first bit line mask is used to form a first bit line layer in a first device level. The first bit line layer compri... | 05/17/2011 |
| 7902071 | Method for forming active and gate runner trenches A method for forming a trench-gated field effect transistor (FET) includes the following steps. Using a first mask, defining and simultaneously forming a plurality of active gate trenches and at least one gate runner trench extending to a first depth within a silico... | 03/08/2011 |
| 7833905 | Method of manufacturing a semiconductor integrated circuit device In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately ... | 11/16/2010 |
| 7749902 | Methods of manufacturing semiconductor device Provided is a method of manufacturing a semiconductor device using double patterning. The method includes: forming a first material layer pattern having recesses in a first direction on an object layer and a second material layer pattern formed on the first material... | 07/06/2010 |
| 7749903 | Gate patterning scheme with self aligned independent gate etch A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. ... | 07/06/2010 |
| 7723230 | Method for manufacturing semiconductor device and method for designing photomask pattern A method for designing a photomask pattern is provided. First, all line ends of object patterns are determined with reference to layout data. Then, object patterns, front edge portions, and joints, which are aligned on the same line extending along the Y-axis, are c... | 05/25/2010 |
| 7718530 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device includes forming a gate conductive layer, a first mask layer, a second mask layer, and a third mask layer over a semiconductor substrate that includes a cell region and a peripheral region. The method also includes f... | 05/18/2010 |
| 7659200 | Self-constrained anisotropic germanium nanostructure from electroplating A nanostructure comprising germanium, including wires of less than 1 micron in diameter and walls of less than 1 micron in width, in contact with the substrate and extending outward from the substrate is provided along with a method of preparation. ... | 02/09/2010 |
| 7648912 | ASIC customization with predefined via mask Disclosed herein is an integrated circuit customized by mask programming using custom conducting layers and via layers interspersed with the custom conducting layers, where the via layers are defined by masks designed prior to receiving a custom circuit design. ... | 01/19/2010 |
| 7595266 | Method of manufacturing a semiconductor integrated circuit device In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately ... | 09/29/2009 |
| 7563712 | Method of forming micro pattern in semiconductor device A method of forming a fine pattern in a semiconductor device includes forming an target layer, a hard mask layer and first sacrificial patterns on a semiconductor substrate; forming an insulating layer and a second sacrificial layer on the hard mask layer and the fi... | 07/21/2009 |
| 7550383 | Methods of performing a photolithography process for forming asymmetric patterns and methods of forming a semiconductor device using the same There are provided methods of performing a photolithography process for forming asymmetric semiconductor patterns and methods of forming a semiconductor device using the same. These methods provide a way of forming asymmetric semiconductor patterns on a photoresist ... | 06/23/2009 |
| 7550384 | Semiconductor device and method for forming pattern in the same A method for forming a fine pattern of a semiconductor device includes forming a first hard mask layer over a semiconductor substrate and a second hard mask layer over the first hard mask layer, selectively etching the second hard mask layer and the first hard mask ... | 06/23/2009 |
| 7544613 | Method of manufacturing semiconductor device with an improved wiring layer structure A method of manufacturing a semiconductor device including word lines of memory cells and a pair of select gate lines. A first insulating film, a first conductive film, a second insulating film, and a first resist are sequentially formed above a semiconductor substr... | 06/09/2009 |
| 7538034 | Integrated circuit having a metal element An integrated circuit is disclosed. The integrated circuit includes a substrate, a metal element, the metal element being arranged on the substrate and including a metal material. A composite element is located over to the metal element, the composite element includ... | 05/26/2009 |
| 7531456 | Method of forming self-aligned double pattern Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial... | 05/12/2009 |
| 7531455 | Method for forming storage node contact in semiconductor device using nitride-based hard mask A method for forming a storage node contact in a semiconductor device using a nitride-based hard mask is provided. The method includes: forming an inter-layer oxide layer on a substrate; forming a hard mask containing a nitride material on the inter-layer oxide laye... | 05/12/2009 |
| 7524764 | Method of forming film pattern, device, method of manufacturing the same, electro-optical apparatus, and electronic apparatus A method of forming a film pattern by disposing a functional liquid on a substrate, includes: forming banks on the substrate; disposing the functional liquid in areas partitioned by the banks; and drying the functional liquid disposed on the substrate, wherein the f... | 04/28/2009 |
| 7419894 | Gate electrode and manufacturing method thereof, and semiconductor device and manufacturing method thereof The present invention provides a method of manufacturing a gate electrode in which a fine gate electrode can effectively be manufactured by thickening a resist opening for gate electrodes formed by ordinary electron beam lithography so as to reduce opening dimension... | 09/02/2008 |
| 7393794 | Pattern formation method After forming a resist film including a hygroscopic compound, pattern exposure is performed by selectively irradiating the resist film with exposing light while supplying water onto the resist film. After the pattern exposure, the resist film is developed so as to f... | 07/01/2008 |
| 7381644 | Pulsed PECVD method for modulating hydrogen content in hard mask A method for forming a PECVD deposited ashable hardmask (AHM) with less than 30% H content at a process temperature below 500° C., e.g., about 400° C. produces low H content hard masks having the property of high selectivity of the hard mask film to the underlying... | 06/03/2008 |
| 7368392 | Method of fabricating a gate structure of a field effect transistor having a metal-containing gate electrode A method of etching metals and/or metal-containing compounds using a plasma comprising a bromine-containing gas. In one embodiment, the method is used during fabrication of a gate structure of a field effect transistor having a titanium nitride gate electrode, an ul... | 05/06/2008 |
| 7365441 | Semiconductor device fabricating apparatus and semiconductor device fabricating method A semiconductor device fabricating method comprises a substrate forming step of forming a plurality of separate conductive pads 20 on an adhesive layer included in an adhesive sheet 50, and a semiconductor chip mounting step of bonding semiconductor ch... | 04/29/2008 |
| 7358521 | Lateral phase change memory and method therefor Briefly, in accordance with an embodiment of the invention, a lateral phase change memory and a method to manufacture a phase change memory is provided. The method may include forming a conductor material over a substrate and patterning the conductor material to for... | 04/15/2008 |
| 7351623 | Liquid crystal display device and fabricating method thereof A thin film transistor substrate of a LCD device and a fabricating method thereof are disclosed for simplifying a fabricating process and enlarging a capacitance value of a storage capacitor without any reduction of aperture ratio. The LCD device includes: a double-... | 04/01/2008 |
| 7341890 | Circuit board with built-in electronic component and method for manufacturing the same A circuit board with an built-in electronic component according to the present invention includes an insulating layer, a first wiring pattern provided on a first main surface of the insulating layer, a second wiring pattern provided on a second main surface differen... | 03/11/2008 |
| 7319070 | Semiconductor device fabrication method In a conductive layer fabrication method, a lower resist layer (210) is formed on a semiconductor substrate. A water soluble resin layer (212) is formed over the lower resist layer. Heat treatment is performed so as to produce a cross-linking layer ( | 01/15/2008 |
| 7303949 | High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown ... | 12/04/2007 |
| 7300844 | Method of forming gate of flash memory device A method of forming a gate of a flash memory device, including the steps of forming a tunnel oxide film and a first polysilicon layer in an active region of a semiconductor substrate, an isolation film in the field region, a dielectric layer, a second polysilicon la... | 11/27/2007 |
| 7297636 | Methods for fabricating device features having small dimensions Methods for fabricating devices having small feature sizes are provided. In an exemplary embodiment, a method comprises forming a patterned first mask layer overlying a subject material layer and isotropically etching the patterned first mask layer. A second masking... | 11/20/2007 |
| 7271094 | Multiple shadow mask structure for deposition shadow mask protection and method of making and using same The present invention is a multi-layer shadow mask and method of use thereof. The multi-layer shadow mask includes a sacrificial mask bonded to a deposition mask. The sacrificial mask provides protection against an accumulation of evaporant on the deposition mask wh... | 09/18/2007 |
| 7271093 | Low-carbon-doped silicon oxide film and damascene structure using same A method of forming an interconnect for a semiconductor device using triple hard layers, comprises: forming a first hard layer serving as an etch stop layer on a metal interconnect-formed dielectric layer; forming a second hard layer on the first hard layer; forming... | 09/18/2007 |
| 7253092 | Tungsten plug corrosion prevention method using water Disclosed herein is a method of making integrated circuits. In one embodiment the method includes forming tungsten plugs in the integrated circuit and forming electrically conductive interconnect lines in the integrated circuit after formation of the tungsten plugs.... | 08/07/2007 |
| 7247555 | Method to control dual damascene trench etch profile and trench depth uniformity A method of forming trench openings in a dual damascene trench and via etch process by using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, to solve dual damascene patterning problems, such as, fencing and sub-trench ... | 07/24/2007 |
| 7247556 | Control of wafer warpage during backend processing A method of fabricating an integrated circuit (IC), during which wafer warpage is controlled by appropriately controlling intrinsic stresses in one or more service layers of the layer stack of the IC's multilevel interconnect structure. In one embodiment, each inter... | 07/24/2007 |
| 7229928 | Method for processing a layered stack in the production of a semiconductor device A resist layer is deposited a resist layer on a first layer of a layered stack. The stack also includes a second layer below the first layer. The resist layer is processed with a lithographic method to achieve a first structured resist layer. At least a part of the ... | 06/12/2007 |
| 7205232 | Method of forming a self-aligned contact structure using a sacrificial mask layer Disclosed is a method of forming a self-aligned contact structure using a sacrificial mask layer. The method includes forming a plurality of parallel interconnection patterns on a semiconductor substrate. Each of the interconnection patterns has an interconnection a... | 04/17/2007 |
