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| Number | Title | Issue Date |
| 8168535 | Method fabricating semiconductor device using multiple polishing processes A method of fabricating a phase change memory device includes the use of first, second and third polishing processes. The first polishing process forms a first contact portion using a first sacrificial layer and the second polishing process forms a phase change mate... | 05/01/2012 |
| 8168534 | Methods of fabricating electrodes and uses thereof The present invention relates to methods for fabricating nanoscale electrodes separated by a nanogap, wherein the gap size may be controlled with high precision using a self-aligning aluminum oxide mask, such that the gap width depends upon the thickness of the alum... | 05/01/2012 |
| 8101519 | Mold, manufacturing method of mold, method for forming patterns using mold, and display substrate and display device manufactured by using method for forming patterns The present invention relates to a mold, a manufacturing method of the mold, and a method of forming patterns using the mold. The mold may include a main body having a convex portion and a recess portion, and a polymer layer formed over the main body by processing a... | 01/24/2012 |
| 8097538 | Method of manufacturing semiconductor device A metal member layer on a silicon member layer is patterned. A sidewall film is formed on a surface of the metal member layer. The silicon member layer is patterned to form a structure including the silicon member layer and the metal member layer, the surface of whi... | 01/17/2012 |
| 8084360 | Method of manufacturing semiconductor device In one embodiment, a method of manufacturing a semiconductor device includes forming a first film containing boron (B) on a member to be etched, the member being a semiconductor substrate, or a film formed on the semiconductor substrate, and forming a second film fo... | 12/27/2011 |
| 8076237 | Method and apparatus for 3D interconnect The present invention discloses methods for depositing a material, particularly a conductive material, in cavities of a substrate and forming bonding contacts or pads thereon. An intracavity structure may be utilized in conjunction with embodiments of the present in... | 12/13/2011 |
| 8067311 | Mask and method for fabricating semiconductor device using the same A mask for forming a metal line and a via contact, and a method for fabricating a semiconductor device using the same, minimizes misalignment. The mask includes a first mask region having a dark tone for light shading, a second mask region having a half tone, being ... | 11/29/2011 |
| 8058168 | Method of fabricating semiconductor device having metal-semiconductor compound regions Example embodiments relate to methods of fabricating a semiconductor device having a metal-semiconductor compound region. A method according to example embodiments may include forming semiconductor pillars on a semiconductor substrate. The semiconductor substrate be... | 11/15/2011 |
| 8048802 | Method for forming interlayer insulating film in semiconductor device A method for forming an interlayer insulating film includes providing a semiconductor substrate having a first substrate region with a plurality of metal wiring and a second substrate region having no metal wiring, and then forming an insulating film dummy pattern i... | 11/01/2011 |
| 8034714 | Semiconductor device and method of fabricating the same Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includ... | 10/11/2011 |
| 8008196 | Method to create a metal pattern using a damascene-like process A method of forming a metal pattern on a dielectric layer that comprises forming at least one trench in a dielectric layer formed from a photosensitive, insulative material is disclosed. A conformed metal layer is formed over the dielectric layer and into the at lea... | 08/30/2011 |
| 7994052 | High-density patterning Methods for patterning high-density features are described herein. Embodiments of the present invention provide a method comprising patterning a first subset of a pattern, the first subset configured to form a plurality of lines over the substrate, and patterning a ... | 08/09/2011 |
| 7994053 | Patterning method of metal oxide thin film using nanoimprinting, and manufacturing method of light emitting diode A method for forming a metal oxide thin film pattern using nanoimprinting according to one embodiment of the present invention includes: coating a photosensitive metal-organic material precursor solution on a substrate; pressurizing the photosensitive metal-organic ... | 08/09/2011 |
| 7972959 | Self aligned double patterning flow with non-sacrificial features Embodiments of the present invention pertain to methods of forming features on a substrate using a self-aligned double patterning (SADP) process. A conformal layer of non-sacrificial material is formed over features of sacrificial structural material patterned near ... | 07/05/2011 |
| 7964503 | Methods of patterning photoresist, and methods of forming semiconductor constructions The invention includes semiconductor constructions containing optically saturable absorption layers. An optically saturable absorption layer can be between photoresist and a topography, with the topography having two or more surfaces of differing reflectivity relati... | 06/21/2011 |
| 7947601 | Semiconductor devices and methods for forming patterned radiation blocking on a semiconductor device Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for manufacturing a microelectronic imager having a die including an image sensor, an integrated circuit electric... | 05/24/2011 |
| 7923371 | Method of manufacturing semiconductor device having contact plugs A semiconductor device has a semiconductor substrate in which a plurality of device regions and a plurality of device isolation regions are alternately formed to extend in a first direction; and a plurality of contact plugs formed on the semiconductor substrate, con... | 04/12/2011 |
| 7833904 | Methods for fabricating nanoscale electrodes and uses thereof The present invention relates to methods for fabricating nanoscale electrodes separated by a nanogap, wherein the gap size may be controlled with high precision using a self-aligning aluminum oxide mask, such that the gap width depends upon the thickness of the alum... | 11/16/2010 |
| 7816262 | Method and algorithm for random half pitched interconnect layout with constant spacing An embodiment of a system and method produces a random half pitched interconnect layout. A first normal-pitch mask and a second normal-pitch mask are created from a metallization layout having random metal shapes. The lines and spaces of the first mask are printed a... | 10/19/2010 |
| 7811934 | Method of manufacturing nanoelectrode lines using nanoimprint lithography process Provided are a method of manufacturing nanoelectrode lines. The method includes the steps of: sequentially forming an insulating layer, a first photoresist layer, and a drop-shaped second photoresist on a substrate; disposing an imprint mold having a plurality of mo... | 10/12/2010 |
| 7741218 | Conductive via formation utilizing electroplating A method for forming a conductive via is discussed and includes forming a seed layer over a first side of a semiconductor substrate, wherein the semiconductor substrate includes a first side opposite a second side, forming a via hole in a semiconductor substrate fro... | 06/22/2010 |
| 7737033 | Etchant and method for fabricating electric device including thin film transistor using the same The present embodiments relate to an etchant and a method of fabricating an electric device including a thin film transistor. The etchant includes a fluorine ion (F−) source, hydrogen peroxide (H2O2), a sulfate, a phosphate, an azo... | 06/15/2010 |
| 7727889 | Method for forming fine pattern by spacer patterning technology In a method for forming a fine pattern, a target layer to be patterned is formed on a semiconductor substrate and a polysilicon layer is formed on the target layer. A partition is then formed on the polysilicon layer with an amorphous carbon layer pattern. A spacer ... | 06/01/2010 |
| 7662715 | Thin film transistor array panel and method for manufacturing the same The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobi... | 02/16/2010 |
| 7632755 | Method for forming an intermetal dielectric layer using low-k dielectric material and a semiconductor device manufactured thereby Disclosed are: (i) a method for forming an intermetal dielectric layer between metal wirings using a low-k dielectric material, and (ii) a semiconductor device with an intermetal dielectric layer comprising a low-k dielectric material. The method comprises the steps... | 12/15/2009 |
| 7595265 | Semiconductor device and method for forming a metal line in the semiconductor device Contact resistance of a semiconductor device may be reduced, and thereby the reliability of the semiconductor device may be enhanced, when a metal line is formed in a semiconductor device according to a method including: (i) forming a metal layer on a semiconductor ... | 09/29/2009 |
| 7563711 | Method of forming a carbon nanotube-based contact to semiconductor Manufacturers encounter limitations in forming low resistance ohmic electrical contact to semiconductor material P-type Gallium Nitride (p-GaN), commonly used in photonic applications, such that the contact is highly transparent to the light emission of the device. ... | 07/21/2009 |
| 7544612 | Method and structure for reducing the effect of vertical steps in patterned layers in semiconductor structures According to an exemplary embodiment, a method for fabricating a multilayer semiconductor structure includes forming first and second patterned segments, where a first patterned segment sidewall is separated from a second patterned segment sidewall by a first gap; f... | 06/09/2009 |
| 7534723 | Methods of forming fine patterns, and methods of forming trench isolation layers using the same Methods of forming a fine pattern include forming an underlying layer on a substrate, forming preliminary hard mask patterns having a first pitch on the underlying layer, the preliminary hard mask patterns having a first width and being spaced apart from each other ... | 05/19/2009 |
| 7528069 | Fine pitch interconnect and method of making Fine pitch contacts are achieved by using traces that extend to the contacts without requiring capture pads at the contact pads. Capture pads are desirably avoided because they have a diameter greater than the line to which they are attached. Preferably, adjacent co... | 05/05/2009 |
| 7514361 | Selective thin metal cap process A method of creating metal caps on copper lines within an inter-line dielectric (ILD) deposits a thin (e.g., 5 nm) metal blanket film (e.g., Ta/TaN) on top the copper lines and dielectric, after the wafer has been planarized. Further a thin dielectric cap is formed ... | 04/07/2009 |
| 7510969 | Electrode line structure having fine line width and method of forming the same In an electrode line structure of a semiconductor device and a method for forming the same, the electrode line structure comprises a semiconductor substrate, and electrode lines, which are formed on the semiconductor substrate, and have an inclined end in the long a... | 03/31/2009 |
| 7491644 | Manufacturing process for a transistor made of thin layers A process for fabricating a transistor that includes a gate located in the immediate proximity of a dielectric includes a step of etching a layer of gate material. The gate etching step includes plasma etching of the gate layer over the major portion of its thicknes... | 02/17/2009 |
| 7482271 | Manufacturing method for electronic substrate, manufacturing method for electro-optical device, and manufacturing method for electronic device A manufacturing method for an electronic substrate, includes: preparing a substrate and a mask having a predetermined region; forming a wiring pattern on the substrate; forming an aperture portion in the predetermined region of the mask; affixing the mask on the sub... | 01/27/2009 |
| 7443019 | Semiconductor device with conductor tracks between semiconductor chip and circuit carrier and method for producing the same The invention relates to a semiconductor device with conductor tracks between a semiconductor chip and a circuit carrier, and to a method for producing the same. The conductor tracks extend from contact areas on the top side of the semiconductor chip to contact pads... | 10/28/2008 |
| 7439177 | Method of manufacturing semiconductor device for improving contact hole filling characteristics while reducing parasitic capacitance of inter-metal dielectric In manufacturing a semiconductor device, a metal film is formed on a semiconductor substrate, and a high-temperature amorphous carbon film pattern for defining a wiring forming area is formed on the metal film. The metal film is etched by using the high-temperature ... | 10/21/2008 |
| 7435681 | Methods of etching stacks having metal layers and hard mask layers Methods which comprise: providing a stack to be etched, the stack comprising a metal interconnect layer disposed above a substrate, a barrier layer disposed above the metal interconnect layer, a hard mask layer disposed on the barrier layer, and a patterning layer d... | 10/14/2008 |
| 7432197 | Methods of patterning photoresist, and methods of forming semiconductor constructions The invention includes semiconductor constructions containing optically saturable absorption layers. An optically saturable absorption layer can be between photoresist and a topography, with the topography having two or more surfaces of differing reflectivity relati... | 10/07/2008 |
| 7432199 | Method of fabricating semiconductor device having reduced contact resistance Provided is a method for fabricating a semiconductor device having reduced contact resistance. In the method, gate patterns defining a narrow opening and a wide opening are formed having an upper portion of a predetermined region of a semiconductor substrate. After ... | 10/07/2008 |
| 7429530 | Method of forming a pattern, method of forming wiring, semiconductor device, TFT device, electro-optic device, and electronic instrument A method of forming a pattern of a functional layer on a surface of a substrate, where a pattern region, to which the pattern is provided, is edged with a boundary layer, and has a first region and a second region communicated with the first region and having a narr... | 09/30/2008 |
