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| Number | Title | Issue Date |
| 8148264 | Methods for fabrication of high aspect ratio micropillars and nanopillars Methods for fabrication of high aspect ratio micropillars and nanopillars are described. Use of alumina as an etch mask for the fabrication methods is also described. The resulting micropillars and nanopillars are analyzed and a characterization of the etch mask is ... | 04/03/2012 |
| 7955975 | Semiconductor element and display device using the same Provided is a semiconductor element including: a semiconductor having an active layer; a gate insulating film which is in contact with the semiconductor, a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film ... | 06/07/2011 |
| 7910479 | Method of manufacturing a photodiode array with through-wafer vias A method for manufacturing a photodiode array includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has a first layer of a first conductivity proximate the first main surface and a seco... | 03/22/2011 |
| 7807569 | Method of manufacturing a contact structure for a semiconductor device In one embodiment, a semiconductor device comprises a conductive pad formed in a semiconductor substrate. The semiconductor device further includes a conductive pattern overlying a peripheral region of the conductive pad. The conductive pattern has an opening to exp... | 10/05/2010 |
| 7589019 | Memory cell array and method of forming a memory cell array A memory cell array includes a plurality of first conductive lines running in a first direction, where the first conductive lines have a pitch Bp, a plurality of second conductive lines, and a plurality of memory cells. Each of the memory cells are at least partiall... | 09/15/2009 |
| 7579273 | Method of manufacturing a photodiode array with through-wafer vias A method for manufacturing a photodiode array includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has a first layer of a first conductivity proximate the first main surface and a seco... | 08/25/2009 |
| 7566658 | Method for fabricating a metal interconnection using a dual damascene process and resulting semiconductor device A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower interconnections, wherein widths of the trenches are greater than widths of the v... | 07/28/2009 |
| 7517799 | Method for forming a plurality of metal lines in a semiconductor device using dual insulating layer A method for forming a plurality of metal lines in a semiconductor device including forming first insulating layer patterns on a semiconductor substrate, the first insulating patterns being spaced from each other; depositing a metal layer on and between the first in... | 04/14/2009 |
| 7507662 | Ferroelectric memory and its manufacturing method A ferroelectric memory includes a substrate, an interlayer dielectric layer composed of at least one layer formed above the substrate, a plurality of ferroelectric capacitors formed above the interlayer dielectric layer, a coating layer that covers the plurality of ... | 03/24/2009 |
| 7442641 | Integrated ball and via package and formation process A method of processing a semiconductor device is provided. The method includes providing a semiconductor device supported by a carrier structure. The carrier structure defines a plurality of vias from a first surface of the carrier structure adjacent the semiconduct... | 10/28/2008 |
| 7419906 | Method for manufacturing a through conductor A method of manufacturing a through conductor that penetrates from an upper surface of a silicon substrate to its lower surface. The through conductor is manufactured in steps which provide a first conductor which extends in the direction of thickness of the silicon... | 09/02/2008 |
| 7413980 | Semiconductor device with improved contact fuse One aspect of the invention provides an integrated circuit (IC). The IC comprises transistors and contact fuses. The contact fuses each comprise a conducting layer, a frustum-shaped contact has a narrower end that contacts the conducting layer and a first metal laye... | 08/19/2008 |
| 7413978 | Substrate, electro-optical device, electronic apparatus, method of forming substrate, method of forming electro-optical device, and method of forming electronic apparatus A contact structure, including: a first conductive layer; a insulating layer formed on the first conductive layer; a second conductive layer formed on the insulating layer; and a columnar structure, buried in a direction of film thickness in the insulating layer, el... | 08/19/2008 |
| 7407884 | Method for forming an aluminum contact A method of forming an aluminum contact including forming a barrier metal layer on an interlayer insulation layer pattern defining a contact hole, and forming an aluminum layer on the barrier metal layer so as to fill the contact hole. The method further includes fo... | 08/05/2008 |
| 7384866 | Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier ... | 06/10/2008 |
| 7381642 | Top layers of metal for integrated circuits The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used... | 06/03/2008 |
| 7375029 | Method for fabricating contact holes in a semiconductor body and a semiconductor structure A method for fabricating contact holes in a semiconductor body proceeds from a structure in which: a plurality of trenches isolated from one another by mesa regions are provided in the semiconductor body, and electrodes are provided in the trenches, which electrodes... | 05/20/2008 |
| 7371602 | Semiconductor package structure and method for manufacturing the same A semiconductor package structure comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an optical component and a plurality of pads disposed on its active surface; pad extension ... | 05/13/2008 |
| 7373226 | System and method for optimizing vehicle diagnostic tress using similar templates A system and method for evaluating and applying edits from one diagnostic tree to another matching or similar diagnostic tree is described. The system includes a diagnostic tree editor, a library, and a comparison engine. These elements work together to convert an O... | 05/13/2008 |
| 7373225 | Method and system for optimizing vehicle diagnostic trees using similar templates A method and system for optimizing vehicle diagnostic trees using similar templates is provided. Diagnostic trees may be modified to include diagnostic code tips or further suggestions or instructions indicating what tool to use or how to use the tool. The diagnosti... | 05/13/2008 |
| 7358170 | Methods of forming conductive interconnects, and methods of depositing nickel The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which contains triethanolamine, maleic anhydride and at least one nickel sa... | 04/15/2008 |
| 7358611 | System and method for adjusting the ratio of deposition times to optimize via density and via fill in aluminum multilayer metallization A system and method is disclosed for adjusting the ratio of deposition times to optimize via density and via fill in an aluminum multilayer metallization process during a manufacturing process of a semiconductor wafer. In a two-step cold/hot aluminum sputtering proc... | 04/15/2008 |
| 7358521 | Lateral phase change memory and method therefor Briefly, in accordance with an embodiment of the invention, a lateral phase change memory and a method to manufacture a phase change memory is provided. The method may include forming a conductor material over a substrate and patterning the conductor material to for... | 04/15/2008 |
| 7298050 | Semiconductor device, method of manufacturing the same, capacitor structure, and method of manufacturing the same A semiconductor device is disclosed that includes an interposer and a semiconductor chip. The interposer includes a Si substrate; multiple through vias provided through an insulating material in corresponding through holes passing through the Si substrate; a thin fi... | 11/20/2007 |
| 7288475 | Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k di... | 10/30/2007 |
| 7279419 | Formation of self-aligned contact plugs Methods of forming a contact structure for semiconductor assemblies are described. One method provides process steps to create an inner dielectric isolation layer after the contact region is protected, which is followed by the formation of the self-aligned contact s... | 10/09/2007 |
| 7271095 | Process for producing metallic interconnects and contact surfaces on electronic components A process produces metallic interconnects and contact surfaces on electronic components using a copper-nickel-gold layer structure. The copper core of the interconnects and contact surfaces is deposited by electroplating by means of a first resist mask made from pos... | 09/18/2007 |
| 7268434 | Semiconductor device and method of manufacturing the same There is disclosed a semiconductor device comprising at least one first insulating film provided above a substrate, being formed with at least one first recess having a first width, and being formed with at least one second recess having a second width which is 1/x ... | 09/11/2007 |
| 7262505 | Selective electroless-plated copper metallization Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on... | 08/28/2007 |
| 7262070 | Method to make a weight compensating/tuning layer on a substrate Embodiments of the present invention form a weight-compensating/tuning layer on a structure (e.g., a silicon wafer with one or more layers of material (e.g., films)) having variations in its surface topology. The variations in surface topology take the form of thick... | 08/28/2007 |
| 7250371 | Reduction of feature critical dimensions A feature in a layer is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls, where the photoresist features have a first critical dimension. A conformal layer is deposited... | 07/31/2007 |
| 7235457 | High permeability layered films to reduce noise in high speed interconnects This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated circuit. The method includes forming a first layer of electrically conduc... | 06/26/2007 |
| 7232762 | Method for forming an improved low power SRAM contact A method of forming contact openings in a semiconductor device including providing a semiconducting substrate; forming an etch stop layer on said semiconducting substrate; forming a dielectric layer on said etch stop layer; forming a bottom anti-reflective coating (... | 06/19/2007 |
| 7211510 | Stacking circuit elements A method of stacking dice in an electronic circuit includes controlling a size of a hole made in a connection pad on each die of said dice to selectively provide an electrical connection to a particular die in the stack. Additionally, a method of stacking dice in an... | 05/01/2007 |
| 7209815 | Test procedures using pictures A method for test procedures using pictures for a vehicle diagnostic system that includes providing text items, examining text items, accessing a database of picture items corresponding to text items, correlating picture items with at least a portion of the text ite... | 04/24/2007 |
| 7199043 | Method of forming copper wiring in semiconductor device Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing proces... | 04/03/2007 |
| 7189645 | System and method for adjusting the ratio of deposition times to optimize via density and via fill in aluminum multilayer metallization A system and method is disclosed for adjusting the ratio of deposition times to optimize via density and via fill in an aluminum multilayer metallization process during a manufacturing process of a semiconductor wafer. In a two-step cold/hot aluminum sputtering proc... | 03/13/2007 |
| 7172966 | Method for fabricating metallic interconnects on electronic components The invention, which relates to a method for fabricating metallic interconnects with copper-nickel-gold layer construction on electronic components, is based on the object of specifying a method by means of which it is possible to fabricate such metallic interconnec... | 02/06/2007 |
| 7173339 | Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon oxide structure with a sidewall terminating at the undoped silicon oxide structure An etchant including C2HxFy, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six, etches doped silicon dioxide with selectivity over both undoped silicon... | 02/06/2007 |
| 7144808 | Integration flow to prevent delamination from copper The present invention provides, in one embodiment, method of forming a barrier layer 300 over a semiconductor substrate 110. The method comprises forming an opening 120 in an insulating layer 130 located over a substrate thereby uncovering an underlying copper layer... | 12/05/2006 |
