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| Number | Title | Issue Date |
| 8187972 | Through-substrate vias with polymer fill and method of fabricating same An through-substrate via fabrication method requires forming a through-substrate via hole in a semiconductor substrate, depositing an electrically insulating, continuous and substantially conformal isolation material onto the substrate and interior walls of the via ... | 05/29/2012 |
| 8173543 | Method of forming hole in semiconductor device using mask The invention provides a method of manufacturing a semiconductor device which achieves high reliability and high yield as well as high production efficiency. Back surface grinding (back grinding) is performed to a semiconductor substrate to thin the semiconductor su... | 05/08/2012 |
| 8168533 | Through-silicon via structure and method for making the same A through-silicon via structure includes a substrate with a first side and a second side, a through-silicon hole connecting the first side and the second side and filled with a conductive material, a passivation layer disposed on and contacting the first side and co... | 05/01/2012 |
| 8158515 | Method of making 3D integrated circuits A method and structure of connecting at least two integrated circuits in a 3D arrangement by a through silicon via which simultaneously connects a connection pad in a first integrated circuit and a connection pad in a second integrated circuit. ... | 04/17/2012 |
| 8158514 | Method for producing vertical electrical contact connections in semiconductor wafers The invention relates to a method for producing vertical electrical connections in semiconductor wafers, the method including the following steps: application of a protective resist to the wafer front side; patterning of the protective resist such that the contacts ... | 04/17/2012 |
| 8153520 | Thinning tungsten layer after through silicon via filling Methods of processing partially manufactured semiconductor substrates with one or more through silicon vias to partially remove a tungsten layer formed on the field region during filling the through silicon vias are provided. In certain embodiments, the methods prod... | 04/10/2012 |
| 8153521 | Wafer-level stack package A wafer-level stack package includes semiconductor chips, first connection members, a second connection member, a substrate and an external connection terminal. The semiconductor chips have a power/ground pad and a signal pad. The first connection members are electr... | 04/10/2012 |
| 8148263 | Methods for forming conductive vias in semiconductor device components A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer,... | 04/03/2012 |
| 8138087 | Method of manufacturing an integrated circuit An integrated circuit is provided that comprises a substrate of silicon and an interconnect in a through-hole extending from the first to the second side of the substrate. The interconnect is coupled to a metallization layer on the first side of the substrate and is... | 03/20/2012 |
| 8129273 | Semiconductor device and method for producing the same In a semiconductor device which has through holes in an end face, in which a semiconductor element is fixedly mounted on a face of a substrate which has a wiring pattern, which is conductive to the wiring portion formed in the through hole, in at least one face, in ... | 03/06/2012 |
| 8129274 | Method for making an aperture in a carrier and electrically connecting two opposite faces of the carrier Disclosed is a method for making an aperture in a carrier and electrically connecting two opposite faces of the carrier. At first, a carrier is provided. Secondly, a heater is provided for heating a portion of the carrier in an environment rich in oxygen, thus makin... | 03/06/2012 |
| 8114772 | Method of manufacturing the semiconductor device A method of manufacturing semiconductor device includes preparing a substrate having a first surface and a second surface opposite to the first surface. A first insulation layer is formed on the second surface. A sacrificial layer is formed on the first insulation l... | 02/14/2012 |
| 8114771 | Semiconductor wafer scale package system A semiconductor wafer scale package system is provided including providing a semiconductor substrate having a through-hole via with a conductive coating, forming a filled via by filling the through-hole via with a conductive material, coupling a package substrate to... | 02/14/2012 |
| 8110500 | Mitigation of plating stub resonance by controlling surface roughness Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the tra... | 02/07/2012 |
| 8110501 | Method of fabricating landing plug with varied doping concentration in semiconductor device A method of fabricating a landing plug in a semiconductor memory device, which in one embodiment includes forming a landing plug contact hole on a semiconductor substrate having an impurity region to expose the impurity region; forming a landing plug by filling the ... | 02/07/2012 |
| 8105944 | Method of designing semiconductor device and method of manufacturing the same A semiconductor device includes a capacitor including a lower electrode and a upper electrode, and a capacitive film formed therebetween; a first via group including one or more first vias which is electrically connected to the lower electrode; and a second via grou... | 01/31/2012 |
| 8093151 | Semiconductor die and method of forming noise absorbing regions between THVS in peripheral region of the die A semiconductor wafer has a plurality of semiconductor die. A peripheral region is formed around the die. An insulating material is formed in the peripheral region. A portion of the insulating material is removed to form a through hole via (THV). A conductive materi... | 01/10/2012 |
| 8062975 | Through substrate vias Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region (26) of a first thickness (27) proximate the front surface (23) of a substrate wafer (20, 20′) by: (i) from th... | 11/22/2011 |
| 8053362 | Method of forming metal electrode of system in package A method for forming a metal electrode of a system in package of a system in package including a multilayer semiconductor device having semiconductor devices stacked in a plurality of layers. The method may include forming a through hole extending through the plural... | 11/08/2011 |
| 8048801 | Substrate with feedthrough and method for producing the same A substrate with first and second main surfaces includes at least one channel extending from the first main surface to the second main surface. The at least one channel includes a first cross-sectional area at a first location and a second cross-sectional area at a ... | 11/01/2011 |
| 8043965 | Method of forming a through substrate via in a compound semiconductor A method is provided for forming a through substrate via in a compound semiconductor having a transistor on a front side of the substrate. The method comprises forming a protective stop pad over a contact area on the front side of the substrate, forming a contact pa... | 10/25/2011 |
| 8039393 | Semiconductor structure, method for manufacturing semiconductor structure and semiconductor package A semiconductor structure, a method for manufacturing a semiconductor structure and a semiconductor package are provided. The method for manufacturing a semiconductor structure includes the following steps. Firstly, a silicon substrate is provided. Next, a part of t... | 10/18/2011 |
| 8034713 | Method for stacking and interconnecting integrated circuits A method for stacking and interconnecting integrated circuits includes providing at least two substrates; forming a trench in each substrate; filling the trench with an insulating material; forming, in each substrate, at least one conductive area; thinning each subs... | 10/11/2011 |
| 8017521 | Semiconductor package having through-hole vias on saw streets formed with partial saw A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer having a plurality of die. A trench is formed between the semiconductor die. The trench extending partially through the semiconductor wafer. The portion of the semi... | 09/13/2011 |
| 8008195 | Method for manufacturing semiconductor device An insulator layer is formed on a part of semiconductor substrate to form an isolation layer that insulates and separates active elements from each other in the first region, and to form a dummy portion which is composed of a base material of the semiconductor subst... | 08/30/2011 |
| 8003532 | Method of using an electroless plating for depositing a metal seed layer for the subsequent plated backside metal film A method of backside metal process for semiconductor electronic devices, particularly of using an electroless plating for depositing a metal seed layer for the plated backside metal film. The backside of a semiconductor wafer, with electronic devices already fabrica... | 08/23/2011 |
| 7998861 | Method of manufacturing through-via Disclosed is a method of manufacturing a through-via. The through-via manufacturing method includes forming a core-via hole in a wafer, forming a suction-via hole adjacent to the core-via hole in the wafer, forming a via core in the core-via hole, forming a polymer-... | 08/16/2011 |
| 7998860 | Method for fabricating semiconductor components using maskless back side alignment to conductive vias A method for fabricating semiconductor components includes the steps of: providing a semiconductor substrate having a circuit side, a back side and conductive vias; removing portions of the substrate from the back side to expose terminal portions of the conductive v... | 08/16/2011 |
| 7998862 | Method for fabricating semiconductor device A method of fabricating a semiconductor device includes forming a via hole in a semiconductor substrate, forming an isolation layer on an inner side of the via hole, forming a diffusion barrier layer over an upper portion of the semiconductor substrate and the inner... | 08/16/2011 |
| 7989345 | Methods of forming blind wafer interconnects, and related structures and assemblies Methods for forming blind wafer interconnects (BWIs) from the back side surface of a substrate structure to the underside of a bond pad on the opposing surface includes the formation of a blind hole from the back side surface, forming a passivating layer therein, re... | 08/02/2011 |
| 7981796 | Methods for forming packaged products An apparatus and methods for packaging semiconductor devices are disclosed. The apparatus is applicable to many types of contemporary packaging schemes that utilize a sacrificial metal base strip. Tunnels formed through an encapsulation area surrounding the device a... | 07/19/2011 |
| 7977239 | Semiconductor device and method for fabricating the same A semiconductor device includes: a first insulation film formed over a semiconductor substrate; and a plurality of first interconnects selectively formed in the first insulation film. A plurality of gaps are formed in part of the first insulation film located betwee... | 07/12/2011 |
| 7968460 | Semiconductor with through-substrate interconnect Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a ... | 06/28/2011 |
| 7964502 | Multilayered through via A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is depo... | 06/21/2011 |
| 7960282 | Method of manufacture an integrated circuit system with through silicon via A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming... | 06/14/2011 |
| 7955974 | Formation of a through-electrode by inkjet deposition of resin pastes When forming a resin material in a through hole, an electrode pad is formed in the bottom portion of the through hole, an insulating material is formed about the periphery of the through hole and a conductive material is formed in the central portion by an inkjet me... | 06/07/2011 |
| 7951709 | Method and apparatus providing integrated circuit having redistribution layer with recessed connectors A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to expose a portion of the stud and then forming a conductive layer inside the trench and in electrical contact wi... | 05/31/2011 |
| 7943514 | Integrated circuits having TSVs including metal gettering dielectric liners An IC includes a substrate having a semiconductor top surface and a bottom surface, wherein the semiconductor top surface includes one or more active circuit components and a plurality of through silicon vias (TSVs) extending through the substrate. The plurality of ... | 05/17/2011 |
| 7943513 | Conductive through connection and forming method thereof A conductive through connection having a body layer and a metal layer is disposed on a semiconductor device, which the metal layer is on a top of body layer and includes a conductive body configured to penetrate the body layer and the metal layer. The width/diameter... | 05/17/2011 |
| 7932180 | Manufacturing a semiconductor device via etching a semiconductor chip to a first layer A method of manufacturing a semiconductor device. The method includes providing a semiconductor chip including contact elements on a first face and a first layer between the first face and a second face opposite the first face. Placing the semiconductor chip on a ca... | 04/26/2011 |
