Bizarre Patents
Method and apparatus for making a drink hop along a bar or counter
A method for generating a drink which appears to hop from a remote spot on the bar or counter and take one or more leaps, before landing in a patron's glass.
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| Number | Title | Issue Date |
| 8129272 | Hidden plating traces A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die whic... | 03/06/2012 |
| 8062974 | Semiconductor device with grounding structure Conductions and vias between different, stacked metallic layers of a semiconductor device may be mechanically damaged by mechanical strain. According to an exemplary embodiment of the present invention, this mechanical strain may be transferred through the layer str... | 11/22/2011 |
| 8043964 | Method for providing electrical connections to spaced conductive lines An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting... | 10/25/2011 |
| 8039392 | Resistor random access memory cell with reduced active area and reduced contact areas A memory device has a sidewall insulating member with a sidewall insulating member length according to a first spacer layer thickness. A first electrode formed from a second spacer layer having a first electrode length according to a thickness of a second spacer lay... | 10/18/2011 |
| 8021981 | Redistribution layers for microfeature workpieces, and associated systems and methods Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a preformed redistribution layer as a unit proximate to and spaced apart from a microf... | 09/20/2011 |
| 8017520 | Method of fabricating a pad over active circuit I.C. with frame support structure An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To pr... | 09/13/2011 |
| 8012874 | Semiconductor chip substrate with multi-capacitor footprint Various methods and apparatus for coupling capacitors to a chip substrate are disclosed. In one aspect, a method of manufacturing is provided that includes forming a mask on a semiconductor chip substrate that has plural conductor pads. The mask has plural openings ... | 09/06/2011 |
| 7964501 | Semiconductor device and method of fabricating the same A method of fabricating a semiconductor device includes providing a semiconductor substrate including a first landing plug and a second landing plug. A bit line is formed over the semiconductor substrate. The bit line is electrically coupled to the first landing plu... | 06/21/2011 |
| 7955973 | Method and apparatus for improvements in chip manufacture and design A method of securing a bond pad in to a semiconductor chip having an upper top metal surface which includes one or more holes, the method comprising the steps of forming a passivation layer over the upper metal surface, which passivation layer has holes therein subs... | 06/07/2011 |
| 7947600 | Manufacturing method for micro-transformers A micro-transformer manufacturing method is provided, which can improve throughput, prevent a crack from entering an insulating film between coils, and manufacture the micro-transformer without using a mask material having a high selection ratio. An insulating film ... | 05/24/2011 |
| 7935630 | Wiring structure and wiring designing method A designing method of a semiconductor device having a first wire and a second wire with a plurality of vias includes determining a first life time change rate of the semiconductor device in response to a change in a number of via column, a second life time change ra... | 05/03/2011 |
| 7932178 | Integrated circuit having a plurality of MOSFET devices A method is provided for manufacturing an integrated circuit having a plurality of MOSFET devices, comprising the steps of: providing a plurality of MOSFET devices each having a first and a second structural parameter associated therewith, wherein a value of one of ... | 04/26/2011 |
| 7910478 | Method of manufacturing semiconductor devices A method of manufacturing a semiconductor device, forms connection pads electrically connected to integrated circuit portion formed in a semiconductor substrate, lays an insulating film and a protective film one over another, forms sub-lines electrically connected t... | 03/22/2011 |
| 7838419 | Systems and methods to laminate passives onto substrate A method may include depositing a dielectric layer onto a substrate, removing portions of the dielectric layer to create a plurality of separated non-removed portions of the dielectric layer, depositing one or more passive electronic components into each of the plur... | 11/23/2010 |
| 7811932 | 3-D semiconductor die structure with containing feature and method A die-on-die assembly has a first die (10) and a second die (50). The first die (10) has a first contact extension (28,42) and a peg (32,44,45) extending a first height above the first die. The second die (50) has a second c... | 10/12/2010 |
| 7781338 | Semiconductor device manufacturing method and semiconductor device The present invention provides a method for forming a semiconductor device, which comprises the steps of preparing a semiconductor wafer including an electrode pad, an insulating film formed with a through hole and a bedding metal layer which are formed in a semicon... | 08/24/2010 |
| 7759247 | Manufacturing method of semiconductor device with a barrier layer and a metal layer This invention provides a semiconductor device and a manufacturing method thereof which can minimize deterioration of electric characteristics of the semiconductor device without increasing an etching process. In the semiconductor device of the invention, a pad elec... | 07/20/2010 |
| 7754607 | Method for manufacturing a liquid crystal display A method for manufacturing a liquid crystal display, the method includes steps of depositing a transparent conductive layer, forming a pixel electrode, and four bottom layers, depositing a semiconductor insulation layer on the pixel electrode and the four bottom lay... | 07/13/2010 |
| 7754606 | Shielded capacitor structure A method and apparatus if provided for shielding a capacitor structure formed in a semiconductor device. In a capacitor formed in an integrated circuit, one or more shields are disposed around layers of conductive strips to shield the capacitor. The shields confine ... | 07/13/2010 |
| 7713871 | System for contacting electronic devices and production processes thereof An embodiment of a system for contacting at least one electronic device having a plurality of contact elements is proposed. The system includes a substrate having a main surface and a plurality of contact terminals projecting from the main surface, wherein each cont... | 05/11/2010 |
| 7691745 | Land patterns for a semiconductor stacking structure and method therefor A semiconductor device has a substrate and an encapsulation area on a first surface of the substrate. A first plurality of metal lands is on the first surface of the substrate around a periphery of the encapsulation area. Solder mask coverers portions of the first p... | 04/06/2010 |
| 7651944 | Methods of positioning and/or orienting nanostructures Methods of positioning and orienting nanostructures, and particularly nanowires, on surfaces for subsequent use or integration. The methods utilize mask based processes alone or in combination with flow based alignment of the nanostructures to provide oriented and p... | 01/26/2010 |
| 7642188 | Mixed signal integrated circuit with improved isolation A method for reducing an effective lateral resistance of a buried layer in an IC includes forming first and second circuit sections in a common substrate, the second circuit section being spaced laterally from the first circuit section. The method further includes f... | 01/05/2010 |
| 7622384 | Method of making multi-chip electronic package with reduced line skew A method of making an electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each for having one of the components coupled thereto. The patterns of conta... | 11/24/2009 |
| 7605079 | Manufacturing method for phase change RAM with electrode layer process A method for manufacturing a phase change memory device comprises forming an electrode layer. Electrodes are made in the electrode layer using conductor fill techniques that are also used inter-layer conductors for metallization layers, in order to improve process s... | 10/20/2009 |
| 7589018 | Method of forming contact hole, method of manufacturing wiring board, method of manufacturing semiconductor device, and method of manufacturing electro-optical device A method of forming a contact hole includes forming a first conductive layer patterned so as to serve as an electrode or a wiring on a substrate, forming an insulation layer on the substrate and the first conductive layer, inserting a cutting instrument into the ins... | 09/15/2009 |
| 7560382 | Embedded interconnects, and methods for forming same The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a f... | 07/14/2009 |
| 7550382 | Manufacturing method of semiconductor device, evaluation method of semiconductor device, and semiconductor device A semiconductor element formed over the same substrate as a TFT, includes a semiconductor film having an impurity region; an insulating film formed over the semiconductor film; an electrode divided into a plurality of parts over the insulating film by spacing a dist... | 06/23/2009 |
| 7517796 | Method for patterning submicron pillars The present invention provides for a method to pattern and etch very small dimension pillars, for example in a memory array. When dimensions of pillars become very small, the photoresist pillars used to pattern them may not have sufficient mechanical strength to sur... | 04/14/2009 |
| 7507661 | Method of forming narrowly spaced flash memory contact openings and lithography masks A method is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device wafer, comprising creating a series of optical features spaced on the lithography mask from one another alon... | 03/24/2009 |
| 7501341 | Interconnect array formed at least in part with repeated application of an interconnect pattern An interconnect array formed at least in part using repeated application of an interconnect pattern is described. The interconnect pattern has at least ten interconnect locations. One of the ten interconnect locations is for a power interconnect. Another one of the ... | 03/10/2009 |
| 7494924 | Method for forming reinforced interconnects on a substrate A method for forming reinforced interconnects or bumps on a substrate includes first forming a support structure on the substrate. A substantially filled capsule is then formed around the support structure to form an interconnect. The interconnect can reach a height... | 02/24/2009 |
| 7446038 | Interlayer interconnect of three-dimensional memory and method for manufacturing the same An interlayer interconnect structure of a three-dimensional memory includes memory cell groups, each composed of a plurality of memory cells and connected to their respective selection transistors, because of special arrangement of lines and first plugs as well as l... | 11/04/2008 |
| 7442619 | Method of forming substantially L-shaped silicide contact for a semiconductor device A method of manufacturing a semiconductor device having a substantially L-shaped silicide element forming a contact is disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In... | 10/28/2008 |
| 7429528 | Method of fabricating a pad over active circuit I.C. with meshed support structure An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To pr... | 09/30/2008 |
| 7425498 | Semiconductor device with dummy electrode A semiconductor device includes a gate electrode having a straight portion, a dummy electrode located at a point on the extension of the straight portion, a stopper insulating film, a sidewall insulating film, an interlayer insulating film, and a linear contact port... | 09/16/2008 |
| 7422975 | Composite inter-level dielectric structure for an integrated circuit A method is provided for making an inter-level dielectric for a microelectronic device formed on a substrate. The method begins by forming first and second spacer layers over a substrate layer. The spacer layers are formed from a sacrificial dielectric material. Nex... | 09/09/2008 |
| 7422980 | Methods of positioning and/or orienting nanostructures Methods of positioning and orienting nanostructures, and particularly nanowires, on surfaces for subsequent use or integration. The methods utilize mask based processes alone or in combination with flow based alignment of the nanostructures to provide oriented and p... | 09/09/2008 |
| 7416976 | Method of forming contacts using auxiliary structures A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a first direction. A plurality of conductive contact structures are provided between the wordlines. The pr... | 08/26/2008 |
| 7416932 | Power composite integrated semiconductor device and manufacturing method thereof A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for reducing ON-resistance. Furthermore, wire bonding connection of the copper... | 08/26/2008 |
