Did You Know...
...that the Band-Aid Bandage was invented by a Johnson & Johnson employee whose wife had cut herself? Earl Dickson's wife was rather accident prone, so he set out to develop a bandage that she could apply without help. He placed a small piece of gauze in the center of a small piece of surgical tape, and what we know today as the Band Aid bandage was born!
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8138086 | Method for manufacturing flash memory device A method of manufacturing a flash memory device and devices thereof, which may be capable of preventing damage to a gate. A method of manufacturing a flash memory device may include preparing a semiconductor substrate having an active region defined by a device sepa... | 03/20/2012 |
| 8124530 | Method of preventing generation of arc during rapid annealing by joule heating Disclosed herein is a rapid annealing method in a mixed structure composed of a heat treatment-requiring material, dielectric layer and conductive layer, comprising that during rapid annealing on a predetermined part of the heat treatment-requiring material, by inst... | 02/28/2012 |
| 8012873 | Method for providing temperature uniformity of rapid thermal annealing A method for annealing a semiconductor device having at least one polysilicon region formed on a substrate, comprises growing dielectric material on the substrate adjacent to the polysilicon region. The method continues by polishing a surface of the dielectric mater... | 09/06/2011 |
| 8003531 | Method for manufacturing flash memory device A method for manufacturing a flash memory device is capable of controlling a phenomenon in which a length of the channel between a source and a drain is decreased due to undercut. The method includes forming a gate electrode comprising a floating gate, an ONO film a... | 08/23/2011 |
| 7960281 | Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively l... | 06/14/2011 |
| 7892971 | Sub-second annealing processes for semiconductor devices An annealing method and apparatus for semiconductor manufacturing is described. The method and apparatus allows an anneal that can span a thermal budget and be tailored to a specific process and its corresponding activation energy. In some cases, the annealing metho... | 02/22/2011 |
| 7879721 | Rapid heating with nanoenergetic materials The present process for rapidly heating and cooling a target material without damaging the substrate upon which it has been deposited. More specifically, target material is coated onto a first substrate. A self-propagating nanoenergetic material is selected that com... | 02/01/2011 |
| 7544610 | Method and process for forming a self-aligned silicide contact The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, ... | 06/09/2009 |
| 7470618 | Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively l... | 12/30/2008 |
| 7442625 | Apparatus for annealing, method for annealing, and method for manufacturing a semiconductor device An apparatus for annealing a substrate includes a substrate stage having a substrate mounting portion configured to mount the substrate; a heat source having a plurality of heaters disposed under the substrate mounting portion, the heaters individually preheating a ... | 10/28/2008 |
| 7410854 | Method of making FUSI gate and resulting structure Generally disclosed is a method of a device comprising forming a polysilicon stack including a first and a second polysilicon layer with an intervening etch stop layer, wherein the first polysilicon layer height is at least one third a height of the polysilicon stac... | 08/12/2008 |
| 7407828 | CMOS image sensor and manufacturing method thereof A gate insulation layer with a high dielectric constant for a CMOS image sensor formed by a damascene process. A silicide layer on a gate electrode layer is formed in both a pixel region and a peripheral circuit region, and a silicide layer on a source/drain region ... | 08/05/2008 |
| 7407884 | Method for forming an aluminum contact A method of forming an aluminum contact including forming a barrier metal layer on an interlayer insulation layer pattern defining a contact hole, and forming an aluminum layer on the barrier metal layer so as to fill the contact hole. The method further includes fo... | 08/05/2008 |
| 7375031 | Technique for forming interconnect structures with reduced electro and stress migration and/or resistivity By improving the purity of metal lines and the crystalline structure, the overall performance of metal lines, especially of highly scaled copper-based semiconductor devices, may be enhanced. The modification of the crystalline structure of the metal lines may be per... | 05/20/2008 |
| 7368303 | Method for temperature control in a rapid thermal processing system A method is disclosed for a multi-zone interference correction processing for a rapid thermal processing (RTP) system. This processing allows for improved calibration/tuning of RTP systems by accounting for zone coupling. The disclosed method includes establishing b... | 05/06/2008 |
| 7354848 | Poly-silicon-germanium gate stack and method for forming the same A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that c... | 04/08/2008 |
| 7348229 | Method of manufacturing a semiconductor device and semiconductor device obtained with such a method The invention relates to a method of manufacturing a semiconductor device (10) with a field effect transistor, in which method a semiconductor body (1) of silicon is provided at a surface thereof with a source region (2) and a drain region (3... | 03/25/2008 |
| 7335596 | Method for fabricating copper-based interconnections for semiconductor device Cu-based interconnections are fabricated in a semiconductor device by depositing a thin film of Cu or Cu alloy on a dielectric film by sputtering, the dielectric film having trenches and/or via holes at least one groove and being arranged on or above a substrate, an... | 02/26/2008 |
| 7335595 | Silicide formation using a low temperature anneal process A silicide 160 is formed in exposed silicon on a semiconductor wafer 10 by a method that includes forming a thin interface layer 140 over the semiconductor wafer 10 and performing a first low temperature anneal to create the silicide 1... | 02/26/2008 |
| 7326644 | Semiconductor device and method of fabricating the same A method of fabricating a semiconductor device, includes (a) forming an oxide film entirely over a silicon substrate on which a MOS transistor is fabricated, (b) carrying out first thermal-annealing to the silicon substrate, (c) removing the oxide film in an area wh... | 02/05/2008 |
| 7326628 | Thin layer transfer method utilizing co-implantation to reduce blister formation and to surface roughness A method for producing a semiconductor structure by conducting controlled co-implanting of at least first and second different atomic species into a donor substrate to create an embrittlement zone which defines a thin layer of donor material to be transferred. Impla... | 02/05/2008 |
| 7319061 | Method for fabricating electronic device In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extensi... | 01/15/2008 |
| 7314812 | Method for reducing the effective thickness of gate oxides by nitrogen implantation and anneal A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for e... | 01/01/2008 |
| 7309651 | Method for improving reliability of copper interconnects Doping copper interconnects (100) with silicon (115) has been shown to improve Electromigration and Via Stress Migration reliability. After copper (118) is deposited by electrochemical deposition and chemically-mechanically polished back, doping... | 12/18/2007 |
| 7285471 | Process for transfer of a thin layer formed in a substrate with vacancy clusters Processes for forming semiconductor structure comprising a transfer layer transferred from a donor substrate are provided in which the resulting structure has improved quality with respect to defects and resulting structures therefrom. For example, a semiconductor o... | 10/23/2007 |
| 7282416 | Method for fabricating electronic device In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extensi... | 10/16/2007 |
| 7279421 | Method and deposition system for increasing deposition rates of metal layers from metal-carbonyl precursors A method and a deposition system for increasing deposition rates of metal layers from metal-carbonyl precursors using CO gas and a dilution gas. The method includes providing a substrate in a process chamber of a processing system, forming a process gas containing a... | 10/09/2007 |
| 7241670 | Method to form relaxed SiGe layer with high Ge content using co-implantation of silicon with boron or helium and hydrogen A method of forming a relaxed SiGe layer having a high germanium content in a semiconductor device includes preparing a silicon substrate; depositing a strained SiGe layer; implanting ions into the strained SiGe layer, wherein the ions include silicon ions and ions ... | 07/10/2007 |
| 7238611 | Salicide process A salicide process is provided. A metal layer selected from a group consisting of titanium, cobalt, platinum, palladium and an alloy thereof is formed over a silicon layer. A first thermal process is performed. Next, a second thermal process is performed, wherein th... | 07/03/2007 |
| 7229920 | Method of fabricating metal silicide layer A method of fabricating a metal silicide layer over a substrate is provided. First, a hard mask layer is formed over a gate formed on a substrate and a portion of the substrate is exposed. Thereafter, a first metal silicide layer, which is a cobalt silicide or a tit... | 06/12/2007 |
| 7223675 | Method of forming pre-metal dielectric layer A method of forming a pre-metal dielectric (PMD) layer is disclosed. In the method, after a nitride liner layer is formed on a substrate having a transistor, a USG layer is deposited thereon and then planarized. Next, ion implantation and annealing are performed for... | 05/29/2007 |
| 7223615 | High emissivity capacitor structure The present invention is directed to controlling wafer temperature during rapid thermal processing. Regions and devices in an integrated circuit may be surrounded, inlayed, and overlaid with high absorptive structures to increase the average absorptivity of a region... | 05/29/2007 |
| 7220672 | Semiconductor device comprising metal silicide films formed to cover gate electrode and source-drain diffusion layers and method of manufacturing the same The invention provides a semiconductor device, and a manufacturing method, comprising a semiconductor substrate, a gate insulating film, a gate electrode, and a source-drain diffusion layer. A silicide film is formed on the gate electrode and the source-drain diffus... | 05/22/2007 |
| 7205231 | Method for in-situ uniformity optimization in a rapid thermal processing system The present invention is directed to a method for thermally processing a substrate in a thermal processing system. The method provides an amount of heat to the substrate and obtains information associated with the substrate when the amount of heat is provided. For e... | 04/17/2007 |
| 7202164 | Method of forming ultra thin silicon oxynitride for gate dielectric applications A method of forming a gate dielectric layer is disclosed. The method comprises the following steps. A substrate is provided having silicon regions containing surfaces upon which gate dielectrics are to be disposed. An oxide is formed over the surfaces. A silicon lay... | 04/10/2007 |
| 7199043 | Method of forming copper wiring in semiconductor device Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing proces... | 04/03/2007 |
| 7186569 | Conductive memory stack with sidewall A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in cont... | 03/06/2007 |
| 7183204 | Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an NMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively l... | 02/27/2007 |
| 7183203 | Method of plating a metal or metal compound on a semiconductor substrate that includes using the same main component in both plating and etching solutions A method of forming a copper oxide film including forming a copper oxide film including an ammonia complex by causing a mixed solution of aqueous ammonia and aqueous hydrogen peroxide, which has been adjusted to have pH of 8 to 10 or pH of 9 to 10, to contact a surf... | 02/27/2007 |
| 7172962 | Method of manufacturing a semiconductor device On a substrate are sequentially formed a first interconnection 203, a diffusion barrier film 205 and a second insulating film 207, and on the upper surface of the second insulating film 207 is then formed a sacrificial film 213. Ne... | 02/06/2007 |
