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| Number | Title | Issue Date |
| 7435679 | Alloyed underlayer for microelectronic interconnects Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during... | 10/14/2008 |
| 7394150 | Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a termin... | 07/01/2008 |
| 7358181 | Method for structuring a semiconductor device A method for structuring a laterally extending first layer in a semiconductor device with the aid of a reactive second layer, which together with the first layer to be structured forms first reaction products, which products are removed by material removal that acts... | 04/15/2008 |
| 7323418 | Etch-back process for capping a polymer memory device The present invention leverages an etch-back process to provide an electrode cap for a polymer memory element. This allows the polymer memory element to be formed within a via embedded in layers formed on a substrate. By utilizing the etch-back process, the present ... | 01/29/2008 |
| 7205230 | Process for manufacturing a wiring board having a via A process for manufacturing a wiring board comprising a substrate made of an insulation material and having first and second surfaces, first and second conductor patterns formed on the first and second surfaces, respectively, and a via conductor penetrating the subs... | 04/17/2007 |
| 7186643 | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated cir... | 03/06/2007 |
| 7183193 | Integrated device technology using a buried power buss for major device and circuit advantages A method for providing an improved integrated circuit device is disclosed. The method comprises the steps of providing active and passive areas in the substrate, providing a plurality of slots in the substrate after providing the active and passive areas, and oxidiz... | 02/27/2007 |
| 7129180 | Masking structure having multiple layers including an amorphous carbon layer A masking structure having multiple layers is formed. The masking structure includes an amorphous carbon layer and a cap layer formed over the amorphous carbon layer. The amorphous carbon layer includes transparent amorphous carbon. The cap layer includes non-oxide ... | 10/31/2006 |
| 7115503 | Method and apparatus for processing thin metal layers A method and apparatus for processing a thin metal layer on a substrate to control the grain size, grain shape, and grain boundary location and orientation in the metal layer by irradiating the metal layer with a first excimer laser pulse having an intensity pattern... | 10/03/2006 |
| 7109101 | Capping layer for reducing amorphous carbon contamination of photoresist in semiconductor device manufacture; and process for making same In the fabrication of semiconductor devices using the PECVD process to deposit hardmask material such as amorphous carbon, structure and process are described for reducing migration of species from the amorphous carbon which can damage an overlying photoresist. In o... | 09/19/2006 |
| 7083850 | Electrically conductive thermal interface A porous, flexible, resilient heat transfer material which comprises network of metal flakes. Such heat transfer materials are preferably produced by first forming a conductive paste comprising a volatile organic solvent and conductive metal flakes. The conductive p... | 08/01/2006 |
| 7078772 | Whole chip ESD protection This invention provides two circuit embodiments for a whole chip electrostatic discharge, ECD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output ... | 07/18/2006 |
| 7071124 | Method to reduce PEB sensitivity of resist A method of forming a semiconductor structure, comprises exposing a photoresist layer; followed by heating the photoresist layer to a first temperature for 30 seconds to 3 minutes; followed by heating the photoresist layer to a second temperature for 30 seconds to 3... | 07/04/2006 |
| 7064063 | Photo-thermal induced diffusion Formation of a mixed-material composition through diffusion using photo-thermal energy. The diffusion may be used to create electrically conductive traces. The diffusion may take place between material layers on one of a package substrate, semiconductor substrate, s... | 06/20/2006 |
| 7049230 | Method of forming a contact plug in a semiconductor device A contact plug is formed in a semiconductor device having a silicon substrate having a gate electrode, a junction area and an insulating interlayer. A contact hole is formed to expose the junction area. A plasma process is carried out with respect to a resultant sub... | 05/23/2006 |
| 7033930 | Interconnect structures in a semiconductor device and processes of formation Processes for fabricating a semiconductor device are described herein. In one aspect of the invention, an exemplary process includes forming an interface layer overlying the device substrate, forming a silver layer overlying the interface layer, annealing the substr... | 04/25/2006 |
| 7033960 | Multi-chamber deposition of silicon oxynitride film for patterning Pinholes in a silicon oxynitride film are reduced by PECVD deposition of a plurality of silicon oxynitride sub-layers in a PECVD apparatus containing multiple chambers. Embodiments include forming a layer of amorphous carbon over a conductive layer, such as doped po... | 04/25/2006 |
| 6987070 | Method for forming low-k dielectric layer of semiconductor device Disclosed is a method for forming a low-k dielectric layer of a semiconductor device. The method includes a step providing a semiconductor substrate having a predetermined pattern, a step coating porous powders having a micro size on the semiconductor by spraying th... | 01/17/2006 |
| 6967162 | Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface laye... | 11/22/2005 |
| 6949461 | Method for depositing a metal layer on a semiconductor interconnect structure Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a dielectric layer. The dielectric layer is patterned so as to expose the metal conductor. A liner layer is then... | 09/27/2005 |
| 6946392 | Filling plugs through chemical mechanical polish A scheme for filling plugs through chemical mechanical polishing comprises depositing a malleable conductive layer over a dielectric layer having openings formed therein. The malleable conductive layer is deposited such that a liner is formed within the openings, ho... | 09/20/2005 |
| 6936906 | Integration of barrier layer and seed layer The present invention generally relates to filling of a feature by depositing a barrier layer, depositing a seed layer over the barrier layer, and depositing a conductive layer over the seed layer. In one embodiment, the seed layer comprises a copper alloy seed laye... | 08/30/2005 |
| 6909145 | Metal spacer gate for CMOS FET A method and structure for a metal oxide semiconductor transistor having a substrate, a well region in the substrate, source and drain regions on opposite sides of the well region in the substrate, a gate insulator over the well region of the substrate, a polysilico... | 06/21/2005 |
| 6872643 | Implant damage removal by laser thermal annealing A method of manufacturing a semiconductor device includes forming a layer over a substrate, and doping the layer with a dopant, after which the layer is laser thermal annealed. The layer can be a nitride, an oxide, or a polysilicon layer. The dopants can be arsenic,... | 03/29/2005 |
| 6841473 | Manufacturing an integrated circuit with low solubility metal-conductor interconnect cap A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening forme... | 01/11/2005 |
| 6825114 | Selective stress-inducing implant and resulting pattern distortion in amorphous carbon patterning A method of forming a fuse for use in an integrated circuit using an amorphous carbon mask includes providing a mask material layer comprising amorphous carbon over a conductive layer. The mask material layer is doped with nitrogen, and an anti-reflective coating (A... | 11/30/2004 |
| 6821814 | Method for joining a semiconductor chip to a chip carrier substrate and resulting chip package A method for joining a semiconductor integrated circuit chip in a flip chip configuration, via solder balls, to solderable metal contact pads, leads or circuit lines on the circuitized surface of an organic chip carrier substrate, as well as the resulting chip packa... | 11/23/2004 |
| 6821888 | Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface laye... | 11/23/2004 |
| 6790757 | Wire bonding method for copper interconnects in semiconductor devices The present invention uses wire bonding technology to bond interconnect materials that oxidize easily by using a wire with stable oxidation qualities. A passivation layer is formed on the semiconductor substrate to encapsulate the bonding pad made from the interconn... | 09/14/2004 |
| 6784017 | Method of creating a high performance organic semiconductor device A high temperature thermal annealing process creates a low resistance contact between a metal material and an organic material of an organic semiconductor device, which improves the efficiency of carrier injection. The process forms ohmic contacts and Schottky conta... | 08/31/2004 |
| 6774025 | Method for producing group III nitride compound semiconductor light-emitting element After a p seat electrode is laminated on a light-transmissive electrode, the two electrodes are heated at a relatively low temperature to thereby remove gas (degassing) from between the two electrodes. Then, the two electrodes are alloyed with each other at a high t... | 08/10/2004 |
| 6774035 | Thermal processing of metal alloys for an improved CMP process in integrated circuit fabrication A thermal processing method is described which improves integrated circuit metal polishing and increases conductivity following polish. A method of fabricating a metal layer in an integrated circuit is described which comprises the steps of depositing a layer of met... | 08/10/2004 |
| 6757971 | Filling plugs through chemical mechanical polish A scheme for filling plugs through chemical mechanical polishing comprises depositing a malleable conductive layer over a dielectric layer having openings formed therein. The malleable conductive layer is deposited such that a liner is formed within the openings, ho... | 07/06/2004 |
| 6737287 | Ink used for ink jet, and methods for manufacturing conductive film, electron-emitting device, electron source and image-forming apparatus It is an object of the present invention to manufacture a conductive film with a small shape fluctuation at a high stability and a high reproducibility by using the ink jet system. It is another object of the present invention to provide an electron-emitting device ... | 05/18/2004 |
| 6734047 | Thinning of fuse passivation after C4 formation A method of forming a fuse structure in which passivating material over the fuse has a controlled, substantially uniform thickness that is provided after C4 metallurgy formation. A laser fuse deletion process for the fuse formed by this method is also disclosed.... | 05/11/2004 |
| 6703295 | Method and apparatus for self-doping contacts to a semiconductor The present invention provides a system and method for creating self-doping contacts to silicon devices in which the contact metal is coated with a layer of dopant and subjected to high temperature, thereby alloying the silver with the silicon and simulta... | 03/09/2004 |
| 6670289 | High-pressure anneal process for integrated circuits This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized, sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of... | 12/30/2003 |
| 6569766 | Method for forming a silicide of metal with a high melting point in a semiconductor device A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of forming the metal-silicide layer on the surface of the impurity-diffused... | 05/27/2003 |
| 6551903 | Melt through contact formation method A thin film photovoltaic devices is described, having a glass substrate 11 over which is formed a thin film silicon device having an n++ layer 12, a p layer 13 and a dielectric layer 14 (typically silicon oxide or silicon nitride). To create a ... | 04/22/2003 |
| 6514389 | Method of processing a workpiece A workpiece is processed which includes a multiplicity of recesses formed in the exposed surface. The invention includes depositing a first barrier layer 13 of for example, titanium nitride, a second layer 11 of aluminium alloy and a third relatively thin... | 02/04/2003 |
