Bizarre Patents
Combination Beverage Container and Spittoon
A combination beverage container and spittoon includes a bottom portion including outer wall and a first inner wall defining a spittoon space.
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| Number | Title | Issue Date |
| 8003530 | Method for metallizing semiconductor elements and use thereof The present invention relates to a method for metallizing semiconductor components in which aluminium is used. In particular in the case of products in which the process costs play a big part, such as e.g. solar cells based on silicon, a cost advantage can be achiev... | 08/23/2011 |
| 7968459 | Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) an... | 06/28/2011 |
| 7943511 | Semiconductor process A semiconductor process is provided. First, a substrate having a dielectric layer formed thereon is provided. Thereafter, an interconnection structure including copper is formed in the dielectric layer. Afterwards, a metal layer is formed on the dielectric layer. Th... | 05/17/2011 |
| 7943510 | Methods of processing a substrate and forming a micromagnetic device A method of processing a substrate with a conductive film formed thereover and method of forming a micromagnetic device. In one embodiment, the method of processing the substrate includes reducing a temperature of the substrate to a stress-compensating temperature, ... | 05/17/2011 |
| 7923368 | Junction formation on wafer substrates using group IV nanoparticles A method of forming a diffusion region is disclosed. The method includes depositing a nanoparticle ink on a surface of a wafer to form a non-densified thin film, the nanoparticle ink having set of nanoparticles, wherein at least some nanoparticles of the set of nano... | 04/12/2011 |
| 7902070 | Method and system for producing optically transparent noble metal films A method and system for producing a noble metal film includes the step of sputtering a noble metal on a substrate thus obtaining a film. The method and system further includes the step of subjecting the film to a thermal treatment, thus obtaining the noble metal fil... | 03/08/2011 |
| 7851358 | Low temperature method for minimizing copper hillock defects A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The l... | 12/14/2010 |
| 7816260 | Method for fabricating semiconductor device A method for fabricating a semiconductor device according to the present invention includes: a step for forming a wiring layer on a semiconductor substrate; a step for patterning the wiring layer; and a step for covering the wiring layer with a protective insulating... | 10/19/2010 |
| 7799677 | Device comprising multi-layered thin film having excellent adhesive strength and method for fabricating the same A device comprises a multi-layered thin film having excellent adhesion due to the method of fabricating the same. More particularly, the device includes a multi-layered thin film consisting of a tantalum nitride layer, a tantalum layer formed on the tantalum nitride... | 09/21/2010 |
| 7790612 | Increased grain size in metal wiring structures through flash tube irradiation A method for forming a wiring structure includes forming a metal layer on a substrate, and annealing the metal layer by irradiating the metal layer with light emitted from at least one flash tube, thereby growing crystalline grains of the metal layer. ... | 09/07/2010 |
| 7745330 | Method of carbon nanotube modification Carbon nanotube apparatus, and methods of carbon nanotube modification, include carbon nanotubes having locally modified properties with the positioning of the modifications being controlled. More specifically, the positioning of nanotubes on a substrate with a depo... | 06/29/2010 |
| 7709378 | Method and apparatus for processing thin metal layers A method and apparatus for processing a thin metal layer on a substrate to control the grain size, grain shape, and grain boundary location and orientation in the metal layer by irradiating the metal layer with a first excimer laser pulse having an intensity pattern... | 05/04/2010 |
| 7691743 | Semiconductor device having a capacitance element and method of manufacturing the same A dielectric film is formed by depositing an amorphous strontium oxide film to a thickness of one to several atomic layers on a first electrode layer, then depositing an amorphous titanium oxide film to a thickness of one to several atomic layers on the amorphous st... | 04/06/2010 |
| 7682969 | Method of fabricating semiconductor device A method of forming a semiconductor device that includes heating a wafer on which an Al—Cu sputtering thin film is formed before patterning the Al—Cu sputtering thin film. The heating is performed at a temperature no less than a solid solution temperature of cop... | 03/23/2010 |
| 7666787 | Grain growth promotion layer for semiconductor interconnect structures An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the electromigration problem that is exhibited by prior art interconnect structures, are provided. In accordance with the present invention, ... | 02/23/2010 |
| 7601638 | Interconnect metallization method having thermally treated copper plate film with reduced micro-voids A method for manufacturing a semiconductor device includes forming, on a substrate having a recessed portion on a surface, a plating film which is at least buried in the recessed portion and has a higher impurity concentration in an upper portion than in a lower por... | 10/13/2009 |
| 7538031 | Method of manufacturing a wiring substrate and an electronic instrument A method of manufacturing a wiring substrate having a wiring layer formation step that includes: a first surface processing step in which surface processing is performed on a film formation area of a substrate; a wiring formation step in which a wiring pattern is fo... | 05/26/2009 |
| 7485575 | Method of manufacturing semiconductor device A semiconductor substrate is inserted into a heat treatment apparatus at a low temperature ranging from room temperature to about 50° C., and organic substances included in a metal on the semiconductor substrate are released without carbonization in an annealing pr... | 02/03/2009 |
| 7439137 | Method for manufacturing semiconductor device In a MOSFET, after an element region is formed, a wiring layer is formed subsequently to a barrier metal layer, and hydrogen annealing is performed. However, in the case of an n-channel MOSFET, a threshold voltage is lowered due to an occlusion characteristic of the... | 10/21/2008 |
| 7432173 | Methods of fabricating silicon-on-insulator substrates having a laser-formed single crystalline film In some methods of fabricating a silicon-on-insulator substrate, a semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A first insulating film is formed on the defined region of the semiconductor... | 10/07/2008 |
| 7419907 | Eliminating metal-rich silicides using an amorphous Ni alloy silicide structure The present invention provides a method for producing thin nickel (Ni) monosilicide or NiSi films (having a thickness on the order of about 30 nm or less), as contacts in CMOS devices wherein an amorphous Ni alloy silicide layer is formed during annealing which elim... | 09/02/2008 |
| 7405156 | Method of forming wiring pattern A photoresist pattern is formed on an insulating substrate so that it has a reverse tapered cross section and a reverse pattern of a wiring pattern to be formed. Next, a nanoparticles-containing ink is injected on a wiring region using an inkjet system, followed by ... | 07/29/2008 |
| 7375031 | Technique for forming interconnect structures with reduced electro and stress migration and/or resistivity By improving the purity of metal lines and the crystalline structure, the overall performance of metal lines, especially of highly scaled copper-based semiconductor devices, may be enhanced. The modification of the crystalline structure of the metal lines may be per... | 05/20/2008 |
| 7368173 | Siloxane resin-based anti-reflective coating composition having high wet etch rate Herein we disclose a composition, comprising a siloxane resin having the formula (HSiO3/2)a. (SiO4/2)b(HSiX3/2)c(SiX4/2)d, wherein each X is independently —O—, —OH, or —O... | 05/06/2008 |
| 7368924 | Probe structure having a plurality of discrete insulated probe tips projecting from a support surface, apparatus for use thereof and methods of fabrication thereof The present invention is directed to structures having a plurality of discrete insulated elongated electrical conductors projecting from a support surface which are useful as probes for testing of electrical interconnections to electronic devices, such as integrated... | 05/06/2008 |
| 7364968 | Capacitor in semiconductor device and manufacturing method The capacitor in a semiconductor device includes a substrate, a lower electrode formed over the substrate, a diffusion barrier formed over the lower electrode, a plurality of agglomerates formed over the diffusion barrier, a dielectric layer formed over the surface ... | 04/29/2008 |
| 7365408 | Structure for photolithographic applications using a multi-layer anti-reflection coating A bi-layer anti-reflective coating for use in photolithographic applications, and specifically, for use in ultraviolet photolithographic processes. The bi-layered anti-reflective coating is used to minimize pattern distortion due to reflections from neighboring feat... | 04/29/2008 |
| 7358175 | Serial thermal processor arrangement A serial thermal processing arrangement for treating a wafer of semiconductor material, the steps including: loading the wafer into a chamber at an initial station and purging the chamber with nitrogen gas; introducing formic acid vapor and nitrogen and heating the ... | 04/15/2008 |
| 7354848 | Poly-silicon-germanium gate stack and method for forming the same A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that c... | 04/08/2008 |
| 7352063 | Semiconductor structure that includes a cooling structure formed on a semiconductor surface and method of manufacturing the same A semiconductor device has a semiconductor chip having first and second surfaces; a sealing resin formed over the first surface; and a cooling structure having a first conductive layer formed on the first surface, an n-type semiconductor formed on the first conducti... | 04/01/2008 |
| 7349223 | Enhanced compliant probe card systems having improved planarity Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more ... | 03/25/2008 |
| 7344979 | High pressure treatment for improved grain growth and void reduction A copper film is annealed at high pressure to enhance grain growth and remove voids. Other films, such as dielectrics, may also be suitable. High pressure can be used in conjunction with temperatures lower than room temperature for annealing or higher temperatures m... | 03/18/2008 |
| 7342251 | Method of manufacturing an electro-optical device An object of the invention is to reduce the manufacturing cost of EL display devices and electronic devices incorporating the EL display devices. An EL material is formed by printing in an active matrix EL display device. Relief printing or screen printing may be us... | 03/11/2008 |
| 7335596 | Method for fabricating copper-based interconnections for semiconductor device Cu-based interconnections are fabricated in a semiconductor device by depositing a thin film of Cu or Cu alloy on a dielectric film by sputtering, the dielectric film having trenches and/or via holes at least one groove and being arranged on or above a substrate, an... | 02/26/2008 |
| 7336269 | Electronic discharging control circuit and method thereof for LCD A control circuit and a method discharging capacitor/transistor, for a liquid crystal display (LCD), are provided. The control circuit includes a signal-off detector and an all-gate-on delay cell. When an LCD power-off signal is detected, a first control signal is t... | 02/26/2008 |
| 7335594 | Method for manufacturing a memory device having a nanocrystal charge storage region A method for manufacturing a memory device having a metal nanocrystal charge storage structure. A substrate is provided and a first layer of dielectric material is grown on the substrate. An absorption layer is formed on the first layer of dielectric material. The a... | 02/26/2008 |
| 7326649 | Parylene-based flexible multi-electrode arrays for neuronal stimulation and recording and methods for manufacturing the same Method for manufacturing a parylene-based electrode array that includes an underlying parylene layer, one or more patterned electrode layers comprising a conductive material such as a metal, and one or more overlying parylene layers. The overlying parylene is etched... | 02/05/2008 |
| 7323783 | Electrode, method for producing same and semiconductor device using same There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 se... | 01/29/2008 |
| 7320902 | Electronic device and method of manufacturing the same, chip carrier, circuit board, and electronic instrument An external terminal is formed on an interconnect pattern formed on a substrate by using a soldering material. Subsequently, a chip component having an electrode is mounted on the substrate. An interconnect for electrically connecting the electrode and the interconn... | 01/22/2008 |
| 7320907 | Method for controlling lattice defects at junction and method for forming LDD or S/D regions of CMOS device A method for controlling lattice defects at a junction is described, which is used in accompany with an ion implantation step for forming a junction in a substrate and a subsequent annealing step. In the method, an extra implantation step is performed to increase th... | 01/22/2008 |
