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Wearable Device For Feeding and Observing Birds and Other Flying Animals
A device for feeding and observing flying animals comprising a hat, a support mounted on the hat and extending outward from the hat, and a feeder mounted on the support.
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| Number | Title | Issue Date |
| 8187971 | Method to alter silicide properties using GCIB treatment A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region. ... | 05/29/2012 |
| 7659198 | In-situ deposition for Cu hillock suppression A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wher... | 02/09/2010 |
| 7553763 | Salicide process utilizing a cluster ion implantation process A salicide process contains providing a silicon substrate that comprises at least a predetermined salicide region, performing a cluster ion implantation process to form an amorphized layer in the predetermined salicide region of the silicon substrate near, forming a... | 06/30/2009 |
| 7538030 | Semiconductor device and method of manufacturing same An electrode on a semiconductor substrate includes a polysilicon layer, a silicon implanted layer on the polysilicon layer, a tungsten nitride layer on the silicon implanted layer, a tungsten nitride layer on the silicon implanted layer, and a tungsten layer on the ... | 05/26/2009 |
| 7442640 | Semiconductor device manufacturing methods Methods of manufacturing a semiconductor device including a high-voltage device region and a low-voltage device region are provided. An illustrated method includes forming, on a substrate, a gate pattern for a high-voltage device and a low-voltage device; implanting... | 10/28/2008 |
| 7413992 | Tungsten silicide etch process with reduced etch rate micro-loading The embodiments provides an improved tungsten silicide etching process with reduced etch rate micro-loading effect. In one embodiment, a method for etching a layer formed on a substrate is provided. The method includes providing a substrate into a plasma processing ... | 08/19/2008 |
| 7407884 | Method for forming an aluminum contact A method of forming an aluminum contact including forming a barrier metal layer on an interlayer insulation layer pattern defining a contact hole, and forming an aluminum layer on the barrier metal layer so as to fill the contact hole. The method further includes fo... | 08/05/2008 |
| 7396745 | Formation of ultra-shallow junctions by gas-cluster ion irradiation Method of forming one or more doped regions in a semiconductor substrate and semiconductor junctions formed thereby, using gas cluster ion beams. ... | 07/08/2008 |
| 7393781 | Capping of metal interconnects in integrated circuit electronic devices A multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device, and a method for forming the cap. ... | 07/01/2008 |
| 7378737 | Structures and methods to enhance copper metallization Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a meta... | 05/27/2008 |
| 7371681 | Method of manufacturing a semiconductor device An electrode on a semiconductor substrate includes a polysilicon layer, a silicon-implanted layer on the polysilicon layer, a tungsten nitride layer on the silicon-implanted layer, a tungsten nitride layer on the silicon-implanted layer, and a tungsten layer on the ... | 05/13/2008 |
| 7361538 | Transistors and methods of manufacture thereof Transistors and methods of manufacture thereof are disclosed. A workpiece is provided, a gate dielectric is formed over the workpiece, and a gate is formed over the gate dielectric by exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (... | 04/22/2008 |
| 7348273 | Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device that can inhibit transformation of an NiSi layer into a disilicide is to be provided. An NiSi layer is formed on gate electrodes and source/drain regions in both of a P-MOS transistor and a N-MOS transistor (a silicid... | 03/25/2008 |
| 7329599 | Method for fabricating a semiconductor device Methods are provided for semiconductor devices having low contact resistance. The method in accordance with one embodiment of the invention comprises forming an insulating layer overlying a semiconductor substrate, the semiconductor substrate having a device region ... | 02/12/2008 |
| 7323381 | Semiconductor device and manufacturing method thereof A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of an n channel MIS transistor and a p channel MIS transistor is composed of a... | 01/29/2008 |
| 7304384 | Semiconductor device with a barrier film which contains manganese A semiconductor device includes an interlevel insulating film disposed on a semiconductor substrate and having an opening formed therein. An interconnection main layer, which contains Cu as a main component, is embedded in the opening. A barrier film is interposed b... | 12/04/2007 |
| 7302982 | Label applicator and system A label applicator including a support surface having a central area and curving downwardly from the central area. A post assembly extends up from the central area such that a label having a label through-hole can be positioned in a support position generally on the... | 12/04/2007 |
| 7300871 | Method of doping a conductive layer near a via A method of making a semiconductor device is described. That method comprises forming a conductive layer that contacts a via, such that the conductive layer includes a higher concentration of an electromigration retarding amount of a dopant near the via than away fr... | 11/27/2007 |
| 7297588 | Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities and a process for forming the same One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, ... | 11/20/2007 |
| 7294356 | Performance enhancing coating on intraluminal devices This invention comprises guidewires, stents and other intraluminal devices having a performance enhancing coating deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD). Preferably, a radiopaque coating comprising platinum, tungsten, irid... | 11/13/2007 |
| 7285482 | Method for producing solid-state imaging device A method is provided for producing a solid-state imaging device in which a plurality of pixels are arranged two-dimensionally so as to form a photosensitive region, each of the pixels including a photodiode that photoelectrically converts incident light to store a s... | 10/23/2007 |
| 7268074 | Capping of metal interconnects in integrated circuit electronic devices A multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device, and a method for forming the cap. ... | 09/11/2007 |
| 7268029 | Method of fabricating CMOS transistor that prevents gate thinning Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implante... | 09/11/2007 |
| 7256125 | Method of manufacturing a semiconductor device For improving the reliability of a semiconductor device having a stacked structure of a polycrystalline silicon film and a tungsten silicide film, the device is manufactured by forming a polycrystalline silicon film, a tungsten silicide film and an insulating film s... | 08/14/2007 |
| 7253050 | Transistor device and method of manufacture thereof Methods of forming CMOS devices and structures thereof. A workpiece is provided having a first region and a second region. A high k gate dielectric material is formed over the workpiece. A first gate material comprising a first metal is formed over the high k gate d... | 08/07/2007 |
| 7242012 | Lithography device for semiconductor circuit pattern generator General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 07/10/2007 |
| 7235884 | Local control of electrical and mechanical properties of copper interconnects to achieve stable and reliable via The present invention is a novel method whereby voids or solid opens at the bottom of via can be avoided without drastically altering the resistivity or parasitic capacitances of the whole metal interconnect system. The invention includes in one embodiment a process... | 06/26/2007 |
| 7226859 | Method of forming different silicide portions on different silicon-containing regions in a semiconductor device A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a... | 06/05/2007 |
| 7223691 | Method of forming low resistance and reliable via in inter-level dielectric interconnect A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) la... | 05/29/2007 |
| 7223685 | Damascene fabrication with electrochemical layer removal The present application discloses process comprising providing a wafer, the wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD, and a barrier layer deposited on the under-layer, and a conductive layer depos... | 05/29/2007 |
| 7223696 | Methods for maskless lithography General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 05/29/2007 |
| 7220674 | Copper alloys for interconnections having improved electromigration characteristics and methods of making same Formation of copper alloy interconnect lines on integrated circuits includes introducing dopant elements into a copper layer. Copper alloy interconnect lines may be formed by providing a doping layer over a copper layer, driving dopant material into the copper layer... | 05/22/2007 |
| 7220672 | Semiconductor device comprising metal silicide films formed to cover gate electrode and source-drain diffusion layers and method of manufacturing the same The invention provides a semiconductor device, and a manufacturing method, comprising a semiconductor substrate, a gate insulating film, a gate electrode, and a source-drain diffusion layer. A silicide film is formed on the gate electrode and the source-drain diffus... | 05/22/2007 |
| 7217657 | Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a... | 05/15/2007 |
| 7214614 | System for controlling metal formation processes using ion implantation The present invention is generally directed to various methods of using ion implantation techniques to control various metal formation processes. In one illustrative embodiment, the method comprises forming a metal seed layer above a patterned layer of insulating ma... | 05/08/2007 |
| 7215024 | Barrier-less integration with copper alloy A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the firs... | 05/08/2007 |
| 7199043 | Method of forming copper wiring in semiconductor device Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing proces... | 04/03/2007 |
| 7193239 | Three dimensional structure integrated circuit A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, red... | 03/20/2007 |
| 7186644 | Methods for preventing copper oxidation in a dual damascene process Methods of preventing oxidation of a copper interconnect of a semiconductor device are disclosed. An example method forms a lower copper interconnect on a substrate having at least one predetermined structure, deposits a nitride layer on the lower copper interconnec... | 03/06/2007 |
| 7187057 | Nitrogen controlled growth of dislocation loop in stress enhanced transistor Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to... | 03/06/2007 |
