Did You Know...
...that it was melting ice cream that inspired the invention of the outboard motor? It was a lovely August day and Ole Evinrude was rowing his boat to his favorite island picnic spot. As he rowed, he watched his ice cream melt and wished he had a faster way to get to the island. At that moment the idea for the outboard motor was born!
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| Number | Title | Issue Date |
| 8143158 | Method and device of preventing delamination of semiconductor layers Embodiments of the present invention describe a method and device of preventing delamination of semiconductor layers in a semiconductor device. The semiconductor device comprises a substrate with an interlayer dielectric (ILD). A protection layer is deposited on the... | 03/27/2012 |
| 8003529 | Method of fabrication an integrated circuit A method of forming an integrated circuit is disclosed. The method includes providing a substrate and forming on the substrate a shield structure comprising a shield member and a ground strap. The shield member comprises a non-metallic portion, and the ground strap ... | 08/23/2011 |
| 7935629 | Semiconductor scheme for reduced circuit area in a simplified process An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a ... | 05/03/2011 |
| 7737031 | Insitu formation of inverse floating gate poly structures Briefly, in accordance with one or more embodiments, a method of making an inverse-t shaped floating gate in a non-volatile memory cell or the like is disclosed. ... | 06/15/2010 |
| 7622383 | Methods of forming conductive polysilicon thin films via atomic layer deposition and methods of manufacturing semiconductor devices including such polysilicon thin films A method of forming a conductive polysilicon thin film and a method of manufacturing a semiconductor device using the same are provided. The method of forming a conductive polysilicon thin film may comprise simultaneously supplying a Si precursor having halogen elem... | 11/24/2009 |
| 7432198 | Semiconductor devices and methods of forming interconnection lines therein An example disclosed semiconductor device includes a semiconductor substrate, a lower interlayer insulating layer formed on the substrate, a lower wire formed on the lower interlayer insulating layer, and an upper interlayer insulating layer which is formed on the l... | 10/07/2008 |
| 7425496 | Method for delineating a conducting element disposed on an insulating layer, device and transistor thus obtained A conducting layer is deposited on an insulating layer disposed on a substrate. A mask is formed on at least one area of the conducting layer, thus delineating in the conducting layer at least one complementary area not covered by the mask. The complementary areas o... | 09/16/2008 |
| 7384877 | Technique for reducing silicide defects by reducing deleterious effects of particle bombardment prior to silicidation By reducing the effect of particle bombardment during the sequence for forming a metal silicide in semiconductor devices, the defect rate and the metal silicide uniformity may be enhanced. For this purpose, the metal may be deposited without an immediately preceding... | 06/10/2008 |
| 7371681 | Method of manufacturing a semiconductor device An electrode on a semiconductor substrate includes a polysilicon layer, a silicon-implanted layer on the polysilicon layer, a tungsten nitride layer on the silicon-implanted layer, a tungsten nitride layer on the silicon-implanted layer, and a tungsten layer on the ... | 05/13/2008 |
| 7332420 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device having a P-type MOSFET and an N-type MOSFET, the method comprising the steps of: forming a gate insulating film, a non-doped polysilicon film, a metal silicide film, a metal nitride film and a metal film on a semicon... | 02/19/2008 |
| 7282423 | Method of forming fet with T-shaped gate An FET has a T-shaped gate. The FET has a halo diffusion self-aligned to the bottom portion of the T and an extension diffusion self aligned to the top portion. The halo is thereby separated from the extension implant, and this provides significant advantages. The t... | 10/16/2007 |
| 7256123 | Method of forming an interface for a semiconductor device In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon fr... | 08/14/2007 |
| 7217618 | Semiconductor device and method for fabricating the same using damascene process A semiconductor device and method for fabricating same according to an embodiment of the invention includes: preparing a semiconductor substrate having a first contact pad and a second contact pad; forming a first insulating film on the substrate; etching the first ... | 05/15/2007 |
| 7214602 | Method of forming a conductive structure A method of forming a conductive structure is disclosed. The method includes forming an interconnect in a substrate, and forming a layer of iridium on the interconnect. The layer of iridium has a thickness of less than six hundred angstroms. The method further inclu... | 05/08/2007 |
| 7199043 | Method of forming copper wiring in semiconductor device Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing proces... | 04/03/2007 |
| 7186607 | Charge-trapping memory device and method for production A thin SiGe layer is provided as an additional lower gate electrode layer and is arranged between a thin gate oxide and a gate electrode layer, preferably of polysilicon. The SiGe layer can be etched selectively to the gate electrode and the gate oxide and is latera... | 03/06/2007 |
| 7186612 | Non-volatile DRAM and a method of making thereof A method of forming a non-volatile DRAM includes, in part, forming a first polysilicon layer above a first dielectric layer to form a control gate of the non-volatile device of the non-volatile DRAM; forming sidewall spacers adjacent the first polysilicon layer; for... | 03/06/2007 |
| 7169696 | Method for making a system for selecting one wire from a plurality of wires A system and method for selecting nanometer-scaled devices. The method includes a plurality of semiconductor wires. Two adjacent semiconductor wires of the plurality of semiconductor wires are associated with a separation smaller than or equal to 100 nm. Additionall... | 01/30/2007 |
| 7160801 | Integrated circuit using a dual poly process A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrysta... | 01/09/2007 |
| 7138307 | Method to produce highly doped polysilicon thin films The present invention describes a method of forming a highly doped polysilicon film. According to an embodiment of the present invention, a first silicon film is formed on a substrate. The first silicon film is then doped. Next, a second silicon film is formed on th... | 11/21/2006 |
| 7122863 | SOI device with structure for enhancing carrier recombination and method of fabricating same A semiconductor-on-insulator (SOI) device. The SOI device includes an SOI wafer including an active layer, a substrate and a buried insulation layer disposed therebetween. The buried insulation layer includes an oxide trap region disposed along an upper surface of t... | 10/17/2006 |
| 7091091 | Nonvolatile memory fabrication methods in which a dielectric layer underlying a floating gate layer is spaced from an edge of an isolation trench and/or an edge of the floating gate layer A first dielectric (120) and a first floating gate layer (130.1) are formed on a semiconductor substrate (110). The first dielectric, the first floating gate layer, and the substrate are etched to form isolation trenches (150). The first ... | 08/15/2006 |
| 7071066 | Method and structure for forming high-k gates A method for forming an improved gate stack structure having improved electrical properties in a gate structure forming process A method for forming a high dielectric constant gate structure including providing a silicon substrate comprising exposed surface portions... | 07/04/2006 |
| 7067378 | Methods of fabricating multiple sets of field effect transistors The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, t... | 06/27/2006 |
| 7060570 | Methods of fabricating multiple sets of field effect transistors The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, t... | 06/13/2006 |
| 7060569 | Methods of fabricating multiple sets of field effect transistors The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, t... | 06/13/2006 |
| 7052944 | Thin-film transistor and method of manufacture thereof A thin-film transistor is provided which prevents the degradation of transistor characteristics due to ion channeling. A thin-film transistor (10) includes thin crystalline silicon (2) including source and drain regions (2a) and a channel... | 05/30/2006 |
| 7049230 | Method of forming a contact plug in a semiconductor device A contact plug is formed in a semiconductor device having a silicon substrate having a gate electrode, a junction area and an insulating interlayer. A contact hole is formed to expose the junction area. A plasma process is carried out with respect to a resultant sub... | 05/23/2006 |
| 7041558 | Floating gate memory device and method of manufacturing the same Disclosed herein is a method of forming a floating gate in a non-volatile memory device having a self-aligned shallow trench isolation (SA-STI) structure. First, a tunnel oxide layer is formed on a semiconductor substrate having a SA-STI structure. Next, a first flo... | 05/09/2006 |
| 7029999 | Method for fabricating transistor with polymetal gate electrode The present invention is related to a method for fabricating a transistor with a polymetal gate electrode structure. The method includes the steps of: forming a gate insulation layer on a substrate; forming a patterned gate stack structure on the gate insulation lay... | 04/18/2006 |
| 7029937 | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument A depression is formed from a first surface of a semiconductor substrate. An insulating layer is provided on the bottom surface and an inner wall surface of the depression. A conductive portion is provided inside the insulating layer. A second surface of the semicon... | 04/18/2006 |
| 6995081 | Systems and methods for forming tantalum silicide layers A method of forming (and apparatus for forming) tantalum suicide layers (including tantalum silicon nitride layers), which are typically useful as diffusion barrier layers, on a substrate by using a vapor deposition process with a tantalum halide precursor compound,... | 02/07/2006 |
| 6977204 | Method for forming contact plug having double doping distribution in semiconductor device The present invention provides a method for forming a contact plug in a semiconductor device capable of preventing an increase of contact resistance caused by a decrease in dopant concentration and suppressing diffusions of dopants implanted into the contact. The do... | 12/20/2005 |
| 6977512 | Method and apparatus for characterizing shared contacts in high-density SRAM cell design Test structures are provided for accurately quantifying shared contact resistance. The test structures are built based upon an actual memory cell, which is self-aligning to allow shared contact chains through an array of test cells. A main array of test cells is bui... | 12/20/2005 |
| 6969916 | Substrate having built-in semiconductor apparatus and manufacturing method thereof A substrate having a built-in semiconductor apparatus includes: a semiconductor apparatus which comprises a first semiconductor chip having a first electrode pad formed on a main surface thereof, a protruding portion which is in contact with the first semiconductor ... | 11/29/2005 |
| 6953741 | Methods of fabricating contacts for semiconductor devices utilizing a pre-flow process Methods for fabricating a contact of a semiconductor device are provided by patterning an interlayer dielectric of the semiconductor device to form a contact hole that exposes a silicon-based region of a first impurity type. The exposed silicon-based region is doped... | 10/11/2005 |
| 6939769 | Method for manufacturing a semiconductor device with using double implanting boron and boron difluoride The present invention provides a method for manufacturing a semiconductor device capable of acquiring productivity when a p-type source/drain is formed by the implantation of a BF2 and B ions. The method for manufacturing a semiconductor device includes t... | 09/06/2005 |
| 6930040 | Method of forming a contact on a silicon-on-insulator wafer In a method of the present invention, an intermediate structure having a top surface is provided. An isolation trench is formed is the intermediate structure. Isolation material is deposited over the intermediate structure. The isolation material fills the isolation... | 08/16/2005 |
| 6927135 | Methods of fabricating multiple sets of field effect transistors The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, t... | 08/09/2005 |
| 6919269 | Production method for a semiconductor component A method for fabricating a semiconductor component includes: deposition of a polysilicon layer on a substrate, deposition of a precursor layer on the polysilicon layer, and deposition of a protective layer on the precursor layer. A crystalline transformation occurs ... | 07/19/2005 |
