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| Number | Title | Issue Date |
| 8168532 | Method of manufacturing a multilayer interconnection structure in a semiconductor device A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on ... | 05/01/2012 |
| 8158511 | Method of depositing a uniform barrier layer and metal seed layer with reduced overhang over a plurality of recessed semiconductor features A method of depositing a metal seed layer with underlying barrier layer on a wafer substrate comprising a plurality of recessed device features. A first portion of the barrier layer is deposited on the wafer substrate without excessive build-up of barrier layer mate... | 04/17/2012 |
| 8148261 | Methods of forming metal patterns in openings in semiconductor devices A method of forming a semiconductor device is disclosed. A dielectric layer having a opening therein is formed on a semiconductor substrate. An inner surface of the opening is treated by plasma. A barrier metal layer is formed on the plasma-treated inner surface of ... | 04/03/2012 |
| 8138084 | Electroless Cu plating for enhanced self-forming barrier layers Methods and an apparatus are described for an integrated circuit within which an electroless Cu plated layer having an oxygen content is formed on the top of a seed layer comprising Cu and Mn. The integrated circuit is then exposed to a sufficient high temperature t... | 03/20/2012 |
| 8133810 | Structure for metal cap applications An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive ... | 03/13/2012 |
| 8110498 | Method for passivating exposed copper surfaces in a metallization layer of a semiconductor device When forming sophisticated metallization systems, surface integrity of an exposed metal surface, such as a copper-containing surface, may be enhanced by exposing the surface to a vapor of a passivation agent. Due to the corresponding interaction with the metal surfa... | 02/07/2012 |
| 8105943 | Enhancing structural integrity and defining critical dimensions of metallization systems of semiconductor devices by using ALD techniques During the patterning of sophisticated metallization systems, a damaged surface portion of a sensitive low-k dielectric material may be efficiently replaced by a well-controlled dielectric material, thereby enabling an adaptation of the material characteristics and/... | 01/31/2012 |
| 8101518 | Method and process for forming a self-aligned silicide contact The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, ... | 01/24/2012 |
| 8088687 | Method for forming copper line having self-assembled monolayer for ULSI semiconductor devices A copper line having self assembled monolayer for use in ULSI semiconductor devices and methods of making the same are presented. The copper line includes an interlayer dielectric, a self-assembled monolayer, catalytic particles on the monolayer, and a copper layer ... | 01/03/2012 |
| 8067310 | Semiconductor device and method for manufacturing of same A method for manufacturing a semiconductor device, includes: forming a first metal layer on a semiconductor substrate, the semiconductor substrate including a diffusion layer; forming an insulating layer having an opening on the first metal layer; forming a second m... | 11/29/2011 |
| 8039390 | Method of manufacturing semiconductor device The method of manufacturing a semiconductor device according to the present invention includes: a groove forming step of forming a groove in an insulating layer made of an insulating material containing Si and O; an alloy film applying step of covering the side surf... | 10/18/2011 |
| 8003527 | Manufacturing method of semiconductor device A semiconductor device manufacturing method includes forming an interlayer dielectric film above a semiconductor substrate; forming a first wiring trench with a first width and a second wiring trench with a second width that is larger than the first width inr the in... | 08/23/2011 |
| 7989343 | Method of depositing a uniform metal seed layer over a plurality of recessed semiconductor features We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a first portion of a copper seed layer on a wafer substrate without excessive build-up on the openings of e... | 08/02/2011 |
| 7981793 | Method of forming a metal directly on a conductive barrier layer by electrochemical deposition using an oxygen-depleted ambient By suppressing the presence of free oxygen during a cleaning process and a subsequent electrochemical deposition of a seed layer, the quality of a corresponding interface between the barrier material and the seed layer may be enhanced, thereby also improving perform... | 07/19/2011 |
| 7981794 | Film forming method and substrate processing apparatus A barrier layer including a titanium film is formed at a low temperature, and a TiSix film is self-conformably formed at the interface between the titanium film and the base. In forming the TiSix film 507, the following steps are repeate... | 07/19/2011 |
| 7951708 | Copper interconnect structure with amorphous tantalum iridium diffusion barrier A method of forming a diffusion barrier for use in semiconductor device manufacturing includes depositing, by a physical vapor deposition (PVD) process, an iridium doped, tantalum based barrier layer over a patterned interlevel dielectric (ILD) layer, wherein the ba... | 05/31/2011 |
| 7919409 | Materials for adhesion enhancement of copper film on diffusion barriers We have used the state-of-the-art computational chemistry techniques to identify adhesion promoting layer materials that provide good adhesion of copper seed layer to the adhesion promoting layer and the adhesion promoting layer to the barrier layer. We have identif... | 04/05/2011 |
| 7915162 | Method of forming damascene filament wires A method of forming a semiconductor device. A first dielectric layer is deposited on and in direct mechanical contact with the substrate. A first hard mask is deposited on the first dielectric layer. A first and second trench is formed within the first dielectric la... | 03/29/2011 |
| 7858519 | Integrated circuit and manufacturing method of copper germanide and copper silicide as copper capping layer A method is provided for forming a capping layer comprising Cu, N, and also Si and/or Ge onto a copper conductive structure, said method comprising the sequential steps of: forming, at a temperature range between 200° C. up to 400° C., at least one capping layer o... | 12/28/2010 |
| 7846836 | Method of forming a conductive structure in a semiconductor device and method of manufacturing a semiconductor device A method of forming a conductive structure in a semiconductor device includes forming a conductive layer on a substrate, forming a conductive layer pattern on the substrate by patterning the conductive layer, forming an oxide layer on the substrate and a portion of ... | 12/07/2010 |
| 7829460 | Method of manufracturing increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride By forming an aluminum nitride layer by a self-limiting process sequence, the interface characteristics of a copper-based metallization layer may be significantly enhanced while nevertheless maintaining the overall permittivity of the layer stack at a lower level. | 11/09/2010 |
| 7790611 | Method for FEOL and BEOL wiring A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on ... | 09/07/2010 |
| 7781336 | Semiconductor device including ruthenium electrode and method for fabricating the same A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a fi... | 08/24/2010 |
| 7737030 | Method for manufacturing a semiconductor device, and said semiconductor device A method for manufacturing a semiconductor device has forming a first metal wire in a groove formed in an insulating film on a semiconductor substrate, forming an interlayer dielectric on the insulating film and the first metal wire, forming a via hole by etching th... | 06/15/2010 |
| 7655564 | Method for forming Ta-Ru liner layer for Cu wiring A method of forming a Ta—Ru metal liner layer for Cu wiring includes: (i) conducting atomic deposition of Ta X times, each atomic deposition of Ta being accomplished by a pulse of hydrogen plasma, wherein X is an integer such that a surface of an underlying layer ... | 02/02/2010 |
| 7651943 | Forming diffusion barriers by annealing copper alloy layers A method of forming an interconnect structure of an integrated circuit includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; and forming a copper alloy seed layer in the... | 01/26/2010 |
| 7642187 | Method of forming wiring of a semiconductor memory device A method of forming a wiring for a semiconductor memory device includes obtaining a semiconductor substrate, depositing at least one conductive layer on the semiconductor substrate under controlled conditions, such as substrate temperature and atmosphere temperature... | 01/05/2010 |
| 7629253 | Method for implementing diffusion barrier in 3D memory One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding ... | 12/08/2009 |
| 7576002 | Multi-step barrier deposition method A method of forming barrier layers in a via hole extending through an inter-level dielectric layer and including a preformed first barrier coated onto the bottom and sidewalls of the via holes. In a single plasma sputter reactor, a first step sputters the wafer rath... | 08/18/2009 |
| 7566655 | Integration process for fabricating stressed transistor structure A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition o... | 07/28/2009 |
| 7547629 | Ferroelectric capacitor and its manufacturing method and ferroelectric memory device A method for manufacturing a ferroelectric capacitor includes steps of: (a) forming a first crystalline barrier layer; (b) forming a second crystalline barrier layer composed of nitride by nitriding the first crystalline barrier layer; (c) forming a first electrode ... | 06/16/2009 |
| 7524761 | Method for manufacturing semiconductor device capable of reducing parasitic bit line capacitance A semiconductor memory device is manufactured by: forming a hole by etching an interlayer insulation film formed over a semiconductor substrate; forming a barrier film over the interlayer insulation film including a surface of the hole; forming a first metal film ov... | 04/28/2009 |
| 7473640 | Reactive gate electrode conductive barrier A method, and corresponding transistor structure are provided for protecting the gate electrode from an underlying gate insulator. The method comprises: forming a gate insulator overlying a channel region; forming a first metal barrier overlying the gate insulator, ... | 01/06/2009 |
| 7452807 | Method of forming a metal wiring in a semiconductor device Example embodiments of the present invention relate to a method of forming a metal wiring in a semiconductor device. Other example embodiments of the present invention relate to a method of forming a metal wiring in a semiconductor device without a generation of a b... | 11/18/2008 |
| 7442639 | Method of forming plug of semiconductor device A method for forming a plug of a semiconductor device according to a preferred embodiment includes forming a metal wiring on a semiconductor substrate, forming an interlayer dielectric layer on the semiconductor substrate having the metal wiring, forming a contact h... | 10/28/2008 |
| 7439176 | Semiconductor device multilayer structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method In one embodiment, a semiconductor device comprises a semiconductor substrate and a doped conductive layer formed over the semiconductor substrate. A diffusion barrier layer is formed over the doped conductive layer. The diffusion barrier layer comprises an amorphou... | 10/21/2008 |
| 7435670 | Bit line barrier metal layer for semiconductor device and process for preparing the same The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation layer vapor-deposited on an upper part of a substrate so as to expose a... | 10/14/2008 |
| 7427561 | Method for manufacturing semiconductor device A semiconductor device manufacturing method wherein a metal suicide layer is formed via an in-situ process. The method includes forming a gate electrode on a semiconductor substrate; forming an insulation side wall at either lateral surface of the gate electrode; fo... | 09/23/2008 |
| 7422979 | Method of forming a semiconductor device having a diffusion barrier stack and structure thereof A diffusion barrier stack is formed by forming a layer comprising a metal over a conductor that includes copper; and forming a first dielectric layer over the layer, wherein the dielectric layer is of a thickness that alone it can not serve as a diffusion barrier la... | 09/09/2008 |
| 7420275 | Boron-doped SIC copper diffusion barrier films Copper diffusion barrier films having a boron-doped silicon carbide layer with at least 25% boron by atomic weight of the layer composition have advantages for semiconductor device integration schemes. The films have an integration worthy etch selectivity to carbon ... | 09/02/2008 |
