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| Number | Title | Issue Date |
| 8114770 | Pre-treatment method to increase copper island density of CU on barrier layers A method for producing on-chip interconnect structures on a substrate is provided, comprising at least the steps of providing a substrate and depositing a ruthenium-comprising layer on top of said substrate, and then performing a pre-treatment of the Ru-comprising l... | 02/14/2012 |
| 7704879 | Method of forming low-resistivity recessed features in copper metallization A method is provided for forming low-resistivity recessed features containing a ruthenium (Ru) film integrated with bulk copper (Cu) metal. The method includes providing a patterned substrate containing a recessed feature, depositing a barrier film in the recessed f... | 04/27/2010 |
| 7618890 | Methods for forming conductive structures and structures regarding same A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g. ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boun... | 11/17/2009 |
| 7482269 | Method for controlling the step coverage of a ruthenium layer on a patterned substrate A method for forming a Ru layer for an integrated circuit by providing a patterned substrate in a process chamber, and exposing the substrate to a process gas comprising a ruthenium carbonyl precursor and a CO gas to form a Ru layer over a feature of the patterned s... | 01/27/2009 |
| 7476615 | Deposition process for iodine-doped ruthenium barrier layers An iodine-doped ruthenium barrier layer for use with copper interconnects within integrated circuits is formed using novel, iodine-containing ruthenium precursors in an ALD or CVD process. Ruthenium precursors that may be used include ruthenium containing carbonyls,... | 01/13/2009 |
| 7459392 | Noble metal barrier and seed layer for semiconductors A barrier and seed layer for a semiconductor damascene process is described. The seed layer is formed from a noble metal with an intermediate region between the barrier and noble metal layers to prevent oxidation of the barrier layer. ... | 12/02/2008 |
| 7456101 | Method for enhancing the nucleation and morphology of ruthenium films on dielectric substrates using amine containing compounds Methods for depositing a ruthenium metal layer on a dielectric substrate are provided. The methods involve, for instance, exposing the dielectric substrate to an amine-containing compound, followed by exposing the substrate to a ruthenium precursor and an optional c... | 11/25/2008 |
| 7436066 | Semiconductor element It is an object of the present invention to provide a highly reliable and high-quality semiconductor element by effectively preventing the migration of silver to a nitride semiconductor when an electrode main entirely or mostly of silver having high reflection effic... | 10/14/2008 |
| 7435679 | Alloyed underlayer for microelectronic interconnects Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during... | 10/14/2008 |
| 7435678 | Method of depositing noble metal electrode using oxidation-reduction reaction Provided is a method of depositing a noble metal layer using an oxidation-reduction reaction. The method includes flowing a noble metal source gas, an oxidizing gas, and a reducing gas into a reaction chamber; and generating plasma in the reaction chamber to form a ... | 10/14/2008 |
| 7435605 | Method for fabricating a component having an electrical contact region A method for fabricating a component having an electrical contact region on an n-conducting AlGaInP-based or AlGaInAs-based outer layer of an epitaxially grown semiconductor layer sequence, in which electrical contact material, which includes Au and at least one dop... | 10/14/2008 |
| 7436067 | Methods for forming conductive structures and structures regarding same A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g., ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain bou... | 10/14/2008 |
| 7416974 | Method of manufacturing semiconductor device, and semiconductor device A method of manufacturing a semiconductor device, comprising a first step of forming a layer insulation film on a lower layer wiring provided on a substrate and forming a connection hole in the layer insulation film, a second step of forming an alloy layer composed ... | 08/26/2008 |
| 7416982 | Semiconductor devices and methods for manufacturing the same Semiconductor devices having a copper line layer and methods for manufacturing the same are disclosed. An illustrated semiconductor device comprises a damascene insulating layer having a contact hole, a barrier metal layer including a first ruthenium layer, a ruthen... | 08/26/2008 |
| 7393785 | Methods and apparatus for forming rhodium-containing layers A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula LyRhYz is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and electrodes for c... | 07/01/2008 |
| 7381614 | Method for fabricating a semiconductor memory device that includes silicidizing a portion of a platinum group layer to form a silicide region and selectively removing the silicide region to define a bottom electrode of a capacitor The semiconductor memory device comprises a glue layer defining a cylinder shell, a bottom electrode made of a material of the platinum group and covering the inner face and the outer face of the cylinder shell, a dielectric layer formed over the bottom electrode, a... | 06/03/2008 |
| 7374701 | Organometallic precursor composition and method of forming metal film or pattern using the same A composition of (i) an organometallic precursor containing a hydrazine compound coordinating with a central metal thereof and (ii) an organometallic compound of a main group metal and a method of forming metal film or pattern using this composition. ... | 05/20/2008 |
| 7355256 | MOS Devices with different gate lengths and different gate polysilicon grain sizes A semiconductor device 1 according to the present invention includes a semiconductor substrate 5, a first transistor 10 which is formed on the semiconductor substrate 5 and includes a first gate electrode portion 16 constituted by ... | 04/08/2008 |
| 7341947 | Methods of forming metal-containing films over surfaces of semiconductor substrates The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid. The supercritical fluid has H2, at least one H2-activating catalyst, and at least o... | 03/11/2008 |
| 7329943 | Microelectronic devices and methods for forming interconnects in microelectronic devices Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backs... | 02/12/2008 |
| 7317531 | Apparatus and methods for detecting overlay errors using scatterometry Disclosed are techniques, apparatus, and targets for determining overlay error between two layers of a sample. In one embodiment, a method for determining overlay between a plurality of first structures in a first layer of a sample and a plurality of second structur... | 01/08/2008 |
| 7312127 | Incorporating dopants to enhance the dielectric properties of metal silicates The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. Accor... | 12/25/2007 |
| 7303939 | Electro- and electroless plating of metal in the manufacture of PCRAM devices Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a ... | 12/04/2007 |
| 7288479 | Method for forming a barrier/seed layer for copper metallization A method for improving adhesion of Cu to a Ru layer in Cu metallization. The method includes providing a substrate in a process chamber of a deposition system, depositing a Ru layer on the substrate in a chemical vapor deposition process, and forming a Cu seed layer... | 10/30/2007 |
| 7282387 | Electro- and electroless plating of metal in the manufacture of PCRAM devices Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a ... | 10/16/2007 |
| 7279231 | Electroless plating structure The present invention relates to a cobalt electroless plating bath composition. In one embodiment, the present invention relates to cobalt electroless plating in the fabrication of interconnect structures in semiconductor devices. ... | 10/09/2007 |
| 7273791 | Methods for forming a conductive structure using oxygen diffusion through one metal layer to oxidize a second metal layer A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g. ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boun... | 09/25/2007 |
| 7273814 | Method for forming a ruthenium metal layer on a patterned substrate A method for forming a ruthenium metal layer includes providing a patterned substrate in a process chamber of a deposition system, where the patterned substrate contains one or more vias or trenches, or combinations thereof, depositing a first ruthenium metal layer ... | 09/25/2007 |
| 7271095 | Process for producing metallic interconnects and contact surfaces on electronic components A process produces metallic interconnects and contact surfaces on electronic components using a copper-nickel-gold layer structure. The copper core of the interconnects and contact surfaces is deposited by electroplating by means of a first resist mask made from pos... | 09/18/2007 |
| 7264988 | Electro-and electroless plating of metal in the manufacture of PCRAM devices Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a ... | 09/04/2007 |
| 7262132 | Metal plating using seed film A seed film and methods incorporating the seed film in semiconductor applications is provided. The seed film includes one or more noble metal layers, where each layer of the one or more noble metal layers is no greater than a monolayer. The seed film also includes e... | 08/28/2007 |
| 7253103 | Method for producing semiconductor devices that includes forming a copper film in contact with a ruthenium film Provided is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semic... | 08/07/2007 |
| 7253102 | Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as ... | 08/07/2007 |
| 7244982 | Semiconductor device using a conductive film and method of manufacturing the same A semiconductor device has a capacitive element including a first conductive film formed on the bottom and wall surfaces of an opening formed in an insulating film on a substrate, a dielectric film formed on the first conductive film, and a second conductive film fo... | 07/17/2007 |
| 7238611 | Salicide process A salicide process is provided. A metal layer selected from a group consisting of titanium, cobalt, platinum, palladium and an alloy thereof is formed over a silicon layer. A first thermal process is performed. Next, a second thermal process is performed, wherein th... | 07/03/2007 |
| 7232754 | Microelectronic devices and methods for forming interconnects in microelectronic devices Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backs... | 06/19/2007 |
| 7229913 | Stitched micro-via to enhance adhesion and mechanical strength A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conduct... | 06/12/2007 |
| 7229917 | Film formation method and apparatus for semiconductor process A film-formation method for a semiconductor process includes seed film formation and main film formation. In the seed film formation, a metal-containing raw material gas and a first assist gas to react therewith are supplied into a process container, which accommoda... | 06/12/2007 |
| 7226861 | Methods and apparatus for forming rhodium-containing layers A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula LyRhYz is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and electrodes for c... | 06/05/2007 |
| 7220665 | H plasma treatment Electronic devices are constructed by a method that includes forming a first conductive layer in an opening in a multilayer dielectric structure supported by a substrate, forming a core conductive layer on the first conductive layer, subjecting the core conductive l... | 05/22/2007 |
